wafer.space Run 2

40 public designs on one GF180MCU reticle

Reserve a slot on wafer.space Run 3 Or start with Tiny Tapeout

What was built

The run as a whole: what its designs add up to.

40

Public designs

in 43 of the reticle's 54 slot positions

36

Open source

with a public repository and an open licence

58.5M

Transistors

across the unique designs

2.4M

Logic cells

gates and flip-flops

152 KiB

SRAM

in foundry and custom macros

13

Whole dies

and 30 half and quarter slots

Private designs on the reticle are not in the public layout and are not counted. Designs placed more than once are counted once.

Make a chip of your own

Start small with a Tiny Tapeout tile, or go straight to a whole die on the next wafer.space run.

Make a whole chip of your own

Book a die to itself on wafer.space Run 3: orders close 9 December 2026.

Reserve a slot

Or start with a Tiny Tapeout tile

Tiny Tapeout GF 26c and 26d take projects until 7 December 2026, to be made on wafer.space Run 3.

Submit a project

Get a Tiny Tapeout chip

Every Tiny Tapeout chip comes on a board you can plug in, with all of its projects ready to try.

Buy a chip and board

The reticle

A5 · BTX1 A4 · SCTP A3 · T26A A2 · DCO0 A2 · AS16 A1 · TQVC B5 · CLON B4 · SCMT B3 · T26B B2 · AMM1 B2 · EURO B1 · NAX1 C5 · KIAN C4 · SCUP C2 · AMM1 C2 · OCD3 C1 · CAB1 D5 · T0P3 D4 · SCML D2 · PSOC D2 · 0000 E5 · MOLE E2 · MEME E2 · GD04 F5 · AS04 F4 · WSLG F2 · MEME F2 · GD04 G5 · FS03 G4 · HZ80 G3 · DPK1 G2 · FC01 G2 · CAFE G5 · FS02 G3 · ISHI G2 · SALU G2 · DPK2 G1 · TQVA H5 · FS01 H4 · RLCM H2 · QZ80 H2 · TQVE H1 · TQVD

Every design rendered from the layout at the same scale and placed where it sits on the 30 × 23.4 mm reticle. Dark gaps are private designs or empty slots. Point at a die to see its name, and select it for its details.Every die is listed further down.

Slots

How much of the reticle each design took: a 1 × 1 slot is a whole die of its own, and the ½ sizes are halves and quarters of one. Some designs are placed more than once, so 40 designs fill 43 slots.

Total	43
1 × 1	13
1 × ½	15
½ × 1	7
½ × ½	8

Layout on GitHub The run on Crowd Supply

Shuttle status

Where this run is now, from opening orders to shipping parts.

Done so far

1 March 2026 Campaign opens Run 2 slots available for purchase on Crowd Supply
30 April 2026, 23:59 AoE Early bird deadline Last day to purchase at early bird pricing
30 June 2026, 23:59 AoE Purchase deadline Final deadline to purchase slots
14 July 2026, 23:59 AoE Submission deadline Final deadline to submit clean GDS
22 July 2026 Tape-out to GlobalFoundries GDS files delivered to GlobalFoundries for fabrication
30 July 2026 Masks released Masks approved and fabrication started
17 September 2026 First wafers returned An initial set of wafers back from GlobalFoundries
8 October 2026 First wafers diced The initial wafers cut into individual dies

Still to come

Today, 24 October 2026
22 October 2026 (expected) First dies sorted Dies from the initial wafers picked and sorted by project
22 October 2026 (expected) First bare dies shipped Initial bare dies shipped to customers
12 November 2026 (expected) First packaged parts shipped Initial chip-on-board packaged parts shipped
10 December 2026 (expected) Main wafer lot returned The first full lot of Run 2 wafers back from GlobalFoundries
31 December 2026 (expected) Main lot bare dies shipped Bare dies from the main lot shipped to customers
15 January 2027 (expected) Last wafer lot returned The rest of the Run 2 wafers back from GlobalFoundries
21 January 2027 (expected) Main lot packaged parts shipped Chip-on-board packaged parts from the main lot shipped
5 February 2027 (expected) Last lot bare dies shipped Bare dies from the last lot shipped to customers
26 February 2027 (expected) Last lot packaged parts shipped Chip-on-board packaged parts from the last lot shipped

Missed this run? wafer.space Run 3 takes orders until 9 December 2026: reserve a slot.

From the wafer.space run schedule.

How people used their silicon

Where the area of 40 dies (490 mm² of silicon) actually went

13%

25%

11%

44%

Logic cells 13% — gates and flip-flops doing the design's actual work
SRAM 6% — memory macros
Filler and tap cells 25% — inserted by the tools to keep rows continuous and wells tied
Other 11% — routing channels, analog and custom layout, power grid and empty space
Pad ring 44% — the 442 µm border of I/O cells and bond pads

What people built

The kinds of design on this run.

RISC-V and CPUs 9 Multi-project die 5 Other digital 5 Memory test chip 4 Accelerators 4 Analog and mixed-signal 3 Retro computing 3 Art and logos 2 Test structures 2 FPGA 1 Security 1 Communications 1

Standard cell libraries

The ready-made gate libraries the designs were built from: how many tracks tall each cell is, and the voltage it runs at.

Standard cell library	Logic cells	Share
AS 7t-3.3V gf180mcu_as_sc_mcu7t3v3	1.3M	53%
7t-5V gf180mcu_fd_sc_mcu7t5v0	1.1M	45%
9t-5V gf180mcu_fd_sc_mcu9t5v0	46k	2%
AS extra 7t-5V gf180mcu_as_ex_mcu7t5v0	2k	<1%

Area budget of every design

Each bar is one die, split the same way as above. Sorted by how much of the die is logic.

CLON Cloneless2 MOLE FABulous FPGA SCUP GF180MCU Peripherals BTX1 BTX TQVA TinyQV - Crowdsourced RISC-V SoC DPK2 cordic-romless-x8 TQVE TinyQV - RISC-V SoC with experimental pad setup TQVD TinyQV - RISC-V SoC with HDMI output T26B Tiny Tapeout GF 26b EURO EuroSynth T26A Tiny Tapeout GF 26a DPK1 bio180

Show all 40 dies

CAB1 Cabrera CoB GD04 Racquet Wide 1x0.5 T0P3 Tiny Tapeout GF 0.3 NAX1 Naxos CoB SCTP SlugTPU SCML ML-Audio SC AMM1 raybox-zero wafer.space run 2 half height AS04 Multi-Project die using 3.3V SCL KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version PSOC Simplest possible PicoSoC implementation using wafer.space flow QZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot) SCMT microTheia DCO0 Standard Cell DCO+TDC HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot) WSLG wafer.space Logo AS16 16-bit RISC CPU SALU Simple ALU FS03 Test chip with 5V SRAM blocks FS01 Test chip with 3.3V SRAM blocks using regular design rules FS02 Test chip with 3.3V SRAM blocks using SRAM design rules OCD3 3.3V SRAM test 2 MEME Artwork Meme Chip 0000 ICELab Test Chip FC01 Flip Chip pad test version 1 ISHI ISHI-KAI multi-project die 2 RLCM RLCM: Test Passives For GF180MCUD

Which parts of the process were used

Transistor voltages and optional devices across the 40 designs

Transistor voltages

3.3 V 20

5 V 27

6 V 5

A design counts for a voltage when its standard cells, SRAM or its own transistors use it. 5 V and 6 V transistors share the thick gate oxide; a marker layer in the layout tells them apart.

Optional devices drawn by designers

Device	Designs	Which
High-resistance poly resistors	8	8 designs Multi-Project die using 3.3V SCL, Cabrera CoB, ISHI-KAI multi-project die 2, Naxos CoB, 3.3V SRAM test 2, Tiny Tapeout GF 0.3, Tiny Tapeout GF 26a, TinyQV - RISC-V SoC with HDMI output
MIM capacitors	7	7 designs ICELab Test Chip, Multi-Project die using 3.3V SCL, Cabrera CoB, ISHI-KAI multi-project die 2, Naxos CoB, 3.3V SRAM test 2, RLCM: Test Passives For GF180MCUD
Unsalicided poly resistors	6	Multi-Project die using 3.3V SCL, Cabrera CoB, ISHI-KAI multi-project die 2, Artwork Meme Chip, Naxos CoB, Tiny Tapeout GF 0.3
MOS capacitors	3	Multi-Project die using 3.3V SCL, ISHI-KAI multi-project die 2, Tiny Tapeout GF 0.3
Diodes	3	Multi-Project die using 3.3V SCL, ISHI-KAI multi-project die 2, 3.3V SRAM test 2
Deep N-well	3	ICELab Test Chip, ISHI-KAI multi-project die 2, Tiny Tapeout GF 0.3
Salicided poly resistors	1	Multi-Project die using 3.3V SCL
Diffusion resistors	1	Multi-Project die using 3.3V SCL
Bipolar transistors	1	Tiny Tapeout GF 0.3
Schottky diodes	1	ICELab Test Chip

Not drawn by any design: Native transistors, 10 V LDMOS, N-well resistors, Metal resistors, Well diodes, Zener diodes, eFuses, One-time programmable memory, Inductors.

Only devices outside standard cells, SRAM macros and I/O pads count, since every die has those. A single test structure counts the same as a large block. Faded names have the device only inside a reused block; hover over one to see which.

Gate oxides

Transistors	Own design	With the pad ring	Which (own design)
3.3 V and 5 V/6 V	9	20	9 designs ICELab Test Chip, Cabrera CoB, Test chip with 3.3V SRAM blocks using regular design rules, Test chip with 3.3V SRAM blocks using SRAM design rules, ISHI-KAI multi-project die 2, Naxos CoB, Tiny Tapeout GF 0.3, Tiny Tapeout GF 26a, Tiny Tapeout GF 26b
3.3 V only	11	0	11 designs Multi-Project die using 3.3V SCL, BTX, KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2, FABulous FPGA, 3.3V SRAM test 2, ML-Audio SC, microTheia, SlugTPU, GF180MCU Peripherals, TinyQV - RISC-V SoC with HDMI output, TinyQV - RISC-V SoC with experimental pad setup
5 V/6 V only	18	18	18 designs raybox-zero wafer.space run 2 half height, 16-bit RISC CPU, Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version, Cloneless2, Standard Cell DCO+TDC, bio180, cordic-romless-x8, EuroSynth, Test chip with 5V SRAM blocks, Racquet Wide 1x0.5, FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot), Artwork Meme Chip, Simplest possible PicoSoC implementation using wafer.space flow, FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot), Simple ALU, TinyQV - Crowdsourced RISC-V SoC, TinyQV - Crowdsourced RISC-V SoC (1x0.5), wafer.space Logo

3.3 V transistors have the thin gate oxide; 5 V and 6 V ones share the thick one. "Own design" counts the standard cells, SRAM and transistors the designer chose; "with the pad ring" adds the transistors of the I/O pad cells, measured in each design's pad ring. No transistors of their own: Flip Chip pad test version 1, RLCM: Test Passives For GF180MCUD.

Licences

The licence each designer declared when submitting.

Declared licence	Designs
Apache-2.0	29
MIT	3
CERN-OHL-S-2.0	2
CERN-OHL-P-2.0	2
GPL-3.0-only	1
BSD-3-Clause	1
proprietary	1
GPL-3.0-or-later	1

Some repositories carry a different licence file from the one declared at submission, or none: check a design's repository, and its page here, before reusing it.

Packaging and precheck

How the designs will be packaged, and whether they passed the design-rule checks before manufacture.

24 of 40 designs selected chip-on-board packaging.
39 of 40 designs passed the platform precheck they were accepted on (2026-07-04 to 2026-07-16), and 39 pass their latest re-run; FC01 has no finished precheck recorded.
The KLayout DRC, the sign-off check, is clear in every one of these checks.
The chip-on-board pad mask check passed for all 25 designs that ran it (AS16 switched chip-on-board off after the check it was accepted on).
The advisory Magic DRC reported errors for CAB1, FS01, FS02, FS03, GD04, RLCM, T0P3, T26A, T26B.

What fits on 1 mm² of GF180MCU silicon?

Theoretical maximum against what designers achieved

The maximum packs one cell type edge to edge with no room for wiring. Real designs need the wiring. Each box gives the most of a cell that fits with any GF180MCU library, then with the libraries this run used.

~114k

Inverters per mm²

GF180MCU maximum,
with AS 7t-3.3V inv_2

With this run's libraries:

AS 7t-3.3V: 114k inv_2

7t-5V: 114k inv_1

9t-5V: 89k inv_1

~91k

NAND gates per mm²

GF180MCU maximum,
with 7t-5V nand2_1

With this run's libraries:

AS 7t-3.3V: 65k nand2_2

7t-5V: 91k nand2_1

9t-5V: 71k nand2_1

~76k

Buffers per mm²

GF180MCU maximum,
with AS 7t-3.3V buff_2

With this run's libraries:

AS 7t-3.3V: 76k buff_2

7t-5V: 76k buf_1

9t-5V: 59k buf_1

~17k

Flip-flops per mm²

GF180MCU maximum,
with AS 7t-3.3V dfxtp_2

With this run's libraries:

AS 7t-3.3V: 17k dfxtp_2

7t-5V: 16k dffq_1

9t-5V: 13k dffq_1

AS extra 7t-5V: 14k dfxtp_2

25k

Best core average

logic cells/mm² of core — 33% of the buffer maximum

Cloneless2

34k

Densest mm²

logic cells — 45% of the buffer maximum

GF180MCU Peripherals

8k

Typical die

median logic cells/mm² of core across 34 digital dies (1,000 or more logic cells)

26% of the core covered by logic cells

Percentages compare with the buffer maximum for each design's own library: buffers are among the smallest and most common logic cells, so a design made only of buffers, packed edge to edge with no wiring, would reach 100%.

Sizing your own design

What each slot size held on this run, and what it would hold at its densities

				Logic cells in its digital designs1,000 or more logic cells		Logic cells at this run's density			Theoretical maximum, AS 7t-3.3V cells
Slot	Die	Core area	Designs	Most	Median	Typical8k / mm²	Best25k / mm²	Densest34k / mm²	NAND gatesnand2_2	Flip-flopsdfxtp_2
1 × 1	3.93 × 5.12 mm	12.9 mm²	13	324k	125k	102k	324k	439k	841k	218k
1 × ½	3.93 × 2.53 mm	5.0 mm²	12	68k	36k	40k	126k	170k	326k	85k
½ × 1	1.94 × 5.12 mm	4.5 mm²	7	66k	4k	35k	112k	151k	290k	75k
½ × ½	1.94 × 2.53 mm	1.7 mm²	8	36k	24k	14k	43k	59k	113k	29k

Swipe the table sideways for more columns.

Core area is each design's CORE_AREA, read from its own LibreLane config at the commit that was checked; where that could not be read, the project template's, 442 µm in from each edge of the die. Density inside the seal ring is over the whole die less its 26 µm seal ring: all the silicon a slot gives its designer, pad ring included. "Typical" and "best" multiply the core area by this run's median and best core densities, and "densest" by the densest 1 mm² any design on this run reached; SRAM and analog blocks take their area out of that. The theoretical maxima fill the core with nothing but that one cell of AS 7t-3.3V, the library most used on this run, edge to edge with no routing.

Pick the slot size your design needs on wafer.space Run 3: orders close 9 December 2026.

Logic density of every digital design

A digital die here is one with 1,000 or more logic cells. Solid bar: average over the core. Dark line inside it: average over all the silicon inside the seal ring, pad ring included. Outlined bar: the densest mm² outside SRAM (a dash where memory covers most of the design). The scale ends at the buffer theoretical maximum (76k cells/mm²). The numbers are core / seal ring / densest, in logic cells per mm².

CLON Cloneless2 25k / 16k / 30k TQVA TinyQV - Crowdsourced RISC-V SoC 21k / 8k / 23k BTX1 BTX 20k / 13k / 25k DPK2 cordic-romless-x8 19k / 7k / 21k SCUP GF180MCU Peripherals 19k / 12k / 34k MOLE FABulous FPGA 16k / 11k / 24k DPK1 bio180 15k / 7k / 27k TQVE TinyQV - RISC-V SoC with experimental pad setup 14k / 5k / 16k TQVD TinyQV - RISC-V SoC with HDMI output 14k / 5k / — EURO EuroSynth 14k / 7k / 27k T26B Tiny Tapeout GF 26b 12k / 8k / 25k T26A Tiny Tapeout GF 26a 11k / 7k / 23k

Show all 34 digital dies

CAB1 Cabrera CoB 10k / 5k / 19k NAX1 Naxos CoB 10k / 5k / — SCTP SlugTPU 10k / 6k / 14k T0P3 Tiny Tapeout GF 0.3 9k / 6k / 25k SCML ML-Audio SC 9k / 6k / 13k TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5) 7k / 4k / 16k GD04 Racquet Wide 1x0.5 7k / 4k / 18k AS04 Multi-Project die using 3.3V SCL 7k / 4k / 19k AMM1 raybox-zero wafer.space run 2 half height 6k / 3k / 19k KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 6k / 4k / 15k CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version 5k / 2k / 8k SCMT microTheia 4k / 2k / — PSOC Simplest possible PicoSoC implementation using wafer.space flow 4k / 2k / — QZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot) 3k / 1k / 4k DCO0 Standard Cell DCO+TDC 1k / 1k / 5k HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot) 1k / 1k / 5k WSLG wafer.space Logo 1k / 1k / 11k AS16 16-bit RISC CPU 1k / 1k / 5k SALU Simple ALU 1k / <1k / 2k FS03 Test chip with 5V SRAM blocks 1k / <1k / 2k FS01 Test chip with 3.3V SRAM blocks using regular design rules 1k / <1k / 2k FS02 Test chip with 3.3V SRAM blocks using SRAM design rules 1k / <1k / 2k

Every digital die's densities as a table

Design	Slot	Library	Logic cells	Inside core per mm²	Inside seal ring per mm²	Densest mm² per mm²	Core covered	Core mm²
Cloneless2 CLON	1 × 1	7t-5V	323,612	25,081	16,466	29,930	58%	12.90*
TinyQV - Crowdsourced RISC-V SoC TQVA	½ × ½	7t-5V	35,711	20,611	7,633	22,636	47%	1.73
BTX BTX1	1 × 1	AS 7t-3.3V	252,619	19,579	12,854	24,790	47%	12.90*
cordic-romless-x8 DPK2	½ × ½	7t-5V	33,464	19,314	7,153	21,060	40%	1.73
GF180MCU Peripherals SCUP	1 × 1	AS 7t-3.3V	239,123	18,512	12,167	33,972	53%	12.92
FABulous FPGA MOLE	1 × 1	AS 7t-3.3V	211,813	16,397	10,777	24,122	53%	12.92
bio180 DPK1	½ × 1	7t-5V	66,232	14,856	6,922	26,918	33%	4.46
TinyQV - RISC-V SoC with experimental pad setup TQVE	½ × ½	AS 7t-3.3V	24,213	13,930	5,175	15,896	40%	1.74*
TinyQV - RISC-V SoC with HDMI output TQVD	½ × ½	AS 7t-3.3V	23,689	13,672	5,063	—	37%	1.73
EuroSynth EURO	1 × ½	7t-5V	68,077	13,561	7,084	27,030	34%	5.02
Tiny Tapeout GF 26b T26B	1 × 1	mixed	155,961	12,087	7,935	24,556	35%	12.90*
Tiny Tapeout GF 26a T26A	1 × 1	7t-5V	144,419	11,193	7,348	22,754	33%	12.90*
Cabrera CoB CAB1	1 × ½	7t-5V	52,199	10,398	5,432	18,627	29%	5.02
Naxos CoB NAX1	1 × ½	AS 7t-3.3V	49,919	9,944	5,195	—	27%	5.02
SlugTPU SCTP	1 × 1	AS 7t-3.3V	124,628	9,648	6,341	14,116	26%	12.92
Tiny Tapeout GF 0.3 T0P3	1 × 1	mixed	118,911	9,216	6,050	24,632	27%	12.90*
ML-Audio SC SCML	1 × 1	AS 7t-3.3V	111,492	8,631	5,673	13,251	25%	12.92
TinyQV - Crowdsourced RISC-V SoC (1x0.5) TQVC	1 × ½	7t-5V	36,116	7,194	3,758	16,157	16%	5.02
Racquet Wide 1x0.5 GD04	1 × ½	9t-5V	35,525	7,077	3,697	18,167	28%	5.02
Multi-Project die using 3.3V SCL AS04	1 × 1	AS 7t-3.3V	87,322	6,760	4,443	18,663	18%	12.92
raybox-zero wafer.space run 2 half height AMM1	1 × ½	7t-5V	31,608	6,296	3,289	18,587	19%	5.02
KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 KIAN	1 × 1	AS 7t-3.3V	76,850	5,949	3,910	14,729	16%	12.92
Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version CAFE	½ × ½	7t-5V	8,747	5,048	1,870	7,693	15%	1.73
microTheia SCMT	1 × 1	AS 7t-3.3V	47,523	3,679	2,418	—	7%	12.92
Simplest possible PicoSoC implementation using wafer.space flow PSOC	1 × ½	7t-5V	18,372	3,660	1,912	—	11%	5.02
FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot) QZ80	½ × ½	9t-5V	5,096	2,941	1,089	4,090	10%	1.73
Standard Cell DCO+TDC DCO0	1 × ½	7t-5V	7,139	1,422	743	5,147	6%	5.02
FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot) HZ80	½ × 1	9t-5V	5,143	1,154	537	4,951	4%	4.46
wafer.space Logo WSLG	1 × 1	mixed	14,290	1,106	727	11,110	4%	12.92
16-bit RISC CPU AS16	1 × ½	7t-5V	5,508	1,097	573	5,430	4%	5.02
Simple ALU SALU	½ × ½	7t-5V	1,608	928	344	1,592	3%	1.73
Test chip with 5V SRAM blocks FS03	½ × 1	7t-5V	3,788	847	396	1,789	2%	4.47*
Test chip with 3.3V SRAM blocks using regular design rules FS01	½ × 1	7t-5V	3,540	791	370	1,845	2%	4.47*
Test chip with 3.3V SRAM blocks using SRAM design rules FS02	½ × 1	7t-5V	3,492	781	365	1,807	2%	4.47*

* The project template's core: the design's own config could not be read.

The projects

Every design on this run: an index, then grouped by what it does. Select one for its layout, its measurements and any die photographs.

Design index

All 40 public designs by their code, with the slot each took and how much logic it packs.

Code	Design	Slot	What it is	Logic cells	Cells per mm²
0000	ICELab Test Chip	1 × ½	Analog and mixed-signal	40	<1k
AMM1	raybox-zero wafer.space run 2 half height	1 × ½	Retro computing	31,608	6k
AS04	Multi-Project die using 3.3V SCL	1 × 1	Multi-project die	87,322	7k
AS16	16-bit RISC CPU	1 × ½	RISC-V and CPUs	5,508	1k
BTX1	BTX	1 × 1	Accelerators	252,619	20k
CAB1	Cabrera CoB	1 × ½	Other digital	52,199	10k
CAFE	Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version	½ × ½	Communications	8,747	5k
CLON	Cloneless2	1 × 1	Security	323,612	25k
DCO0	Standard Cell DCO+TDC	1 × ½	Analog and mixed-signal	7,139	1k
DPK1	bio180	½ × 1	RISC-V and CPUs	66,232	15k
DPK2	cordic-romless-x8	½ × ½	Accelerators	33,464	19k
EURO	EuroSynth	1 × ½	Analog and mixed-signal	68,077	14k
FC01	Flip Chip pad test version 1	½ × ½	Test structures	0
FS01	Test chip with 3.3V SRAM blocks using regular design rules	½ × 1	Memory test chip	3,540	1k
FS02	Test chip with 3.3V SRAM blocks using SRAM design rules	½ × 1	Memory test chip	3,492	1k
FS03	Test chip with 5V SRAM blocks	½ × 1	Memory test chip	3,788	1k
GD04	Racquet Wide 1x0.5	1 × ½	RISC-V and CPUs	35,525	7k
HZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot)	½ × 1	Retro computing	5,143	1k
ISHI	ISHI-KAI multi-project die 2	½ × 1	Multi-project die	0
KIAN	KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2	1 × 1	RISC-V and CPUs	76,850	6k
MEME	Artwork Meme Chip	1 × ½	Art and logos	226	<1k
MOLE	FABulous FPGA	1 × 1	FPGA	211,813	16k
NAX1	Naxos CoB	1 × ½	Other digital	49,919	10k
OCD3	3.3V SRAM test 2	1 × ½	Memory test chip	123	<1k
PSOC	Simplest possible PicoSoC implementation using wafer.space flow	1 × ½	RISC-V and CPUs	18,372	4k
QZ80	FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)	½ × ½	Retro computing	5,096	3k
RLCM	RLCM: Test Passives For GF180MCUD	½ × 1	Test structures	0
SALU	Simple ALU	½ × ½	Other digital	1,608	1k
SCML	ML-Audio SC	1 × 1	Accelerators	111,492	9k
SCMT	microTheia	1 × 1	Other digital	47,523	4k
SCTP	SlugTPU	1 × 1	Accelerators	124,628	10k
SCUP	GF180MCU Peripherals	1 × 1	Other digital	239,123	19k
T0P3	Tiny Tapeout GF 0.3	1 × 1	Multi-project die	118,911	9k
T26A	Tiny Tapeout GF 26a	1 × 1	Multi-project die	144,419	11k
T26B	Tiny Tapeout GF 26b	1 × 1	Multi-project die	155,961	12k
TQVA	TinyQV - Crowdsourced RISC-V SoC	½ × ½	RISC-V and CPUs	35,711	21k
TQVC	TinyQV - Crowdsourced RISC-V SoC (1x0.5)	1 × ½	RISC-V and CPUs	36,116	7k
TQVD	TinyQV - RISC-V SoC with HDMI output	½ × ½	RISC-V and CPUs	23,689	14k
TQVE	TinyQV - RISC-V SoC with experimental pad setup	½ × ½	RISC-V and CPUs	24,213	14k
WSLG	wafer.space Logo	1 × 1	Art and logos	14,290	1k

Show all 40 designsShow the first 16 only

Swipe the table sideways for more columns.

Designs that grew

These designs have been made more than once: first as a Tiny Tapeout tile or on a Google shuttle, then on wafer.space, or improved and made again on a later run. Start small, then come back bigger. The ringed marker is this run.

FABulous FPGA MOLE

TinyQV RISC-V SoC TQVA, TQVC, TQVD, TQVE

KianV RISC-V Linux SoC KIAN

raybox-zero AMM1

Open-source Z80 HZ80, QZ80

Avalon Semiconductors' retro-computing family AS04

SERV multi-core RISC-V SoC GD04

Expresso Ethernet switch CAFE

3.3V SRAM test 2 OCD3

wafer.space Logo WSLG

Tiny Tapeout tile Google shuttle wafer.space die this run
Each marker is one version of the design: hover over it or focus it for details, and select it to open its page. On a phone, the table below lists every one.

As a table

Design	Made on	When	Version	Size
FABulous FPGA	Google GFMPW-0	Dec 2022	56C6 One-hot FABulous FPGA	Caravel chip
	wafer.space Run 1	Dec 2025	MOLE FABulous FPGA	1 × 1 slot
	Tiny Tapeout IHP 26a	Mar 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout SKY 26a	May 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout SKY 26b	May 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout GF 0.3	Jun 2026	Tiny FABulous FPGA; Tiny FABulous FPGA (3.3V version)	4 × 4 tiles
	wafer.space Run 2	Jul 2026	MOLE FABulous FPGA	1 × 1 slot
	Tiny Tapeout SKY 26c	Sep 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout IHP 26b	Sep 2026	Tiny FABulous FPGA	6 × 4 tiles
TinyQV RISC-V SoC	Tiny Tapeout 6	Apr 2024	TinyQV RISC-V SoC	2 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	TinyQV RISC-V SoC	2 × 2 tiles
	Tiny Tapeout IHP 25a	Mar 2025	TinyQV RISC-V SoC	3 × 2 tiles
	Tiny Tapeout IHP 25b	Sep 2025	TinyQV - Crowdsourced RISC-V SoC	5 × 4 tiles
	Tiny Tapeout SKY 25a	Sep 2025	TinyQV 'Asteroids' - Crowdsourced RISC-V SoC; TinyQV 'Berzerk' - Crowdsourced RISC-V SoC	8 × 4 tiles, 4 × 4 tiles
	Tiny Tapeout SKY 25b	Nov 2025	TinyQV RISC-V SoC	3 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	TinyQV RISC-V SoC	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	TinyQV RISC-V SoC	3 × 4 tiles
	wafer.space Run 1	Dec 2025	TQVA TinyQV - Crowdsourced RISC-V SoC; TQVB TinyQV - Crowdsourced RISC-V SoC (0.5x1); TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5)	TQVA ½ × ½ slot, TQVB ½ × 1 slot, TQVC 1 × ½ slot
	Tiny Tapeout GF 0.3	Jun 2026	TinyQV RISC-V SoC	4 × 2 tiles
	wafer.space Run 2	Jul 2026	TQVA TinyQV - Crowdsourced RISC-V SoC; TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5); TQVD TinyQV - RISC-V SoC with HDMI output; TQVE TinyQV - RISC-V SoC with experimental pad setup	TQVA ½ × ½ slot, TQVC 1 × ½ slot, TQVD ½ × ½ slot, TQVE ½ × ½ slot
KianV RISC-V Linux SoC	Tiny Tapeout 5	Nov 2023	KianV uLinux SoC	8 × 2 tiles
	Tiny Tapeout 6	Apr 2024	KianV uLinux SoC	8 × 2 tiles
	Tiny Tapeout 7	Jun 2024	KianV RISC-V RV32E Baremetal SoC	3 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	KianV RISC-V RV32E Baremetal SoC	4 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	KianV uLinux SoC	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	KianV uLinux SoC	4 × 4 tiles
	wafer.space Run 1	Dec 2025	KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU	1 × 1 slot
	Tiny Tapeout IHP 26a	Mar 2026	KianV SV32 TT Linux SoC	8 × 4 tiles
	Tiny Tapeout GF 0.3	Jun 2026	KianV uLinux SoC	4 × 4 tiles
	wafer.space Run 2	Jul 2026	KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2	1 × 1 slot
raybox-zero	Tiny Tapeout 4	Sep 2023	raybox-zero	4 × 2 tiles
	Tiny Tapeout 7	Jun 2024	raybox-zero TT07 edition	6 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	raybox-zero TTIHP0p2 edition	4 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	raybox-zero TT07 edition	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	raybox-zero TTGF0p2 edition	3 × 4 tiles
	Tiny Tapeout IHP 0.4	Mar 2026	raybox-zero TTIHP0p4 edition	6 × 2 tiles
	wafer.space Run 2	Jul 2026	AMM1 raybox-zero wafer.space run 2 half height	1 × ½ slot
Open-source Z80	Tiny Tapeout 7	Jun 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout 9	Nov 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout IHP 25a	Mar 2025	Zilog Z80	2 × 2 tiles
	Tiny Tapeout GF 0.2	Nov 2025	Zilog Z80	2 × 2 tiles
	wafer.space Run 1	Dec 2025	HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot); RZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU	HZ80 ½ × 1 slot, RZ80 1 × 1 slot
	wafer.space Run 2	Jul 2026	HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot); QZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)	HZ80 ½ × 1 slot, QZ80 ½ × ½ slot
Avalon Semiconductors' retro-computing family	Tiny Tapeout 2	Dec 2022	Avalon Semiconductors '5401' 4-bit Microprocessor; Avalon Semiconductors 'TBB1143' Programmable Sound Generator	1 × 1 tile
	Google GFMPW-0	Dec 2022	105A AS2650	Caravel chip
	Tiny Tapeout 3	Apr 2023	Avalon Semiconductors '5401' 4-bit Microprocessor; Avalon Semiconductors 'TBB1143' Programmable Sound Generator	1 × 1 tile
	wafer.space Run 1	Dec 2025	AS03 WS-Multi	1 × 1 slot
	wafer.space Run 2	Jul 2026	AS04 Multi-Project die using 3.3V SCL	1 × 1 slot
SERV multi-core RISC-V SoC	Tiny Tapeout 2	Dec 2022	serv - Serial RISC-V CPU	1 × 1 tile
	Google GFMPW-0	Dec 2022	6079 Serv tri-core (GF180 MPW0 Serv)	Caravel chip
	Tiny Tapeout 3	Apr 2023	serv - Serial RISC-V CPU	1 × 1 tile
	wafer.space Run 1	Dec 2025	GD02 Racquet Half r1p0 (1/2 slot); GD03 Racquet r2p0 - 23 core SoC; GD04 Racquet Wide 1x0.5	GD02 ½ × 1 slot, GD03 1 × 1 slot, GD04 1 × ½ slot
	wafer.space Run 2	Jul 2026	GD04 Racquet Wide 1x0.5	1 × ½ slot
Expresso Ethernet switch	Tiny Tapeout GF 0.3	Jun 2026	Until heat death do us part	2 × 2 tiles
	Tiny Tapeout GF 26b	Jun 2026	100Mbps 3 port Ethernet switch; 100Mbps Ethernet Accelerator Wrapper	2 × 2 tiles, 1 × 2 tiles
	wafer.space Run 2	Jul 2026	CAFE Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version	½ × ½ slot
3.3V SRAM test 2	wafer.space Run 1	Dec 2025	OCD2 ocd_sram_test	1 × ½ slot
3.3V SRAM test 2	wafer.space Run 2	Jul 2026	OCD3 3.3V SRAM test 2	1 × ½ slot
wafer.space Logo	wafer.space Run 1	Dec 2025	WSLG wafer.space Logo	1 × 1 slot
wafer.space Logo	wafer.space Run 2	Jul 2026	WSLG wafer.space Logo	1 × 1 slot

3 dies are Tiny Tapeout chips

Tiny Tapeout GF 0.3 (T0P3), Tiny Tapeout GF 26a (T26A) and Tiny Tapeout GF 26b (T26B) each hold dozens of small projects from Tiny Tapeout, the cheaper way to make a first chip. Each has pages of its own, project by project.

Tiny Tapeout chips on wafer.space Submit to the next one, by 7 December 2026

RISC-V and CPUs 9

16-bit RISC CPU

1 × ½ slot · 6k logic cells · 2 SRAM

5 V

bio180

½ × 1 slot · 66k logic cells · 8 SRAM

chip-on-board

5 V

Racquet Wide 1x0.5

1 × ½ slot · 36k logic cells · 6 SRAM

placed 2 times

5 V

KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2

1 × 1 slot · 77k logic cells · 21 SRAM

chip-on-board

3.3 V

Simplest possible PicoSoC implementation using wafer.space flow

1 × ½ slot · 18k logic cells · 8 SRAM

5 V

TinyQV - Crowdsourced RISC-V SoC

½ × ½ slot · 36k logic cells · 1 SRAM

5 V

TinyQV - Crowdsourced RISC-V SoC (1x0.5)

1 × ½ slot · 36k logic cells · 1 SRAM

5 V

TinyQV - RISC-V SoC with HDMI output

½ × ½ slot · 24k logic cells · 5 SRAM

chip-on-board

3.3 V High-resistance poly resistors

TinyQV - RISC-V SoC with experimental pad setup

½ × ½ slot · 24k logic cells · 10 SRAM

3.3 V

Multi-project die 5

Multi-Project die using 3.3V SCL

1 × 1 slot · 87k logic cells

chip-on-board

3.3 V MIM capacitorsMOS capacitorsHigh-resistance poly resistorsUnsalicided poly resistorsSalicided poly resistorsDiffusion resistorsDiodes

ISHI-KAI multi-project die 2

½ × 1 slot · 44k transistors

chip-on-board

3.3 V · 5 V · 6 V MIM capacitorsMOS capacitorsHigh-resistance poly resistorsUnsalicided poly resistorsDiodesDeep N-well

Tiny Tapeout GF 0.3

1 × 1 slot · 119k logic cells · 1 SRAM

3.3 V · 5 V · 6 V MOS capacitorsHigh-resistance poly resistorsUnsalicided poly resistorsDeep N-wellBipolar transistors

Tiny Tapeout GF 26a

1 × 1 slot · 144k logic cells · 2 SRAM

3.3 V · 5 V High-resistance poly resistors

Tiny Tapeout GF 26b

1 × 1 slot · 156k logic cells · custom SRAM

3.3 V · 5 V

Other digital 5

Cabrera CoB

1 × ½ slot · 52k logic cells · 6 SRAM

chip-on-board

3.3 V · 5 V · 6 V MIM capacitorsHigh-resistance poly resistorsUnsalicided poly resistors

Naxos CoB

1 × ½ slot · 50k logic cells · 12 SRAM

chip-on-board

3.3 V · 5 V · 6 V MIM capacitorsHigh-resistance poly resistorsUnsalicided poly resistors

Simple ALU

½ × ½ slot · 2k logic cells

chip-on-board

5 V

microTheia

1 × 1 slot · 48k logic cells · 41 SRAM

chip-on-board

3.3 V

GF180MCU Peripherals

1 × 1 slot · 239k logic cells

chip-on-board

3.3 V

Memory test chip 4

Test chip with 3.3V SRAM blocks using regular design rules

½ × 1 slot · 4k logic cells

chip-on-board

3.3 V · 5 V

Test chip with 3.3V SRAM blocks using SRAM design rules

½ × 1 slot · 3k logic cells · custom SRAM

chip-on-board

3.3 V · 5 V

Test chip with 5V SRAM blocks

½ × 1 slot · 4k logic cells

chip-on-board

5 V

3.3V SRAM test 2

1 × ½ slot · 123 logic cells · 4 SRAM

chip-on-board

3.3 V MIM capacitorsHigh-resistance poly resistorsDiodes

Accelerators 4

BTX

1 × 1 slot · 253k logic cells · 19 SRAM

chip-on-board

3.3 V

cordic-romless-x8

½ × ½ slot · 33k logic cells

chip-on-board

5 V

ML-Audio SC

1 × 1 slot · 111k logic cells · 38 SRAM

chip-on-board

3.3 V

SlugTPU

1 × 1 slot · 125k logic cells · 17 SRAM

chip-on-board

3.3 V

Analog and mixed-signal 3

ICELab Test Chip

1 × ½ slot · 40 logic cells

3.3 V · 5 V · 6 V MIM capacitorsDeep N-wellSchottky diodes

Standard Cell DCO+TDC

1 × ½ slot · 7k logic cells

chip-on-board

5 V

EuroSynth

1 × ½ slot · 68k logic cells

chip-on-board

5 V

Retro computing 3

raybox-zero wafer.space run 2 half height

1 × ½ slot · 32k logic cells

placed 2 timeschip-on-board

5 V

FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot)

½ × 1 slot · 5k logic cells

5 V

FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)

½ × ½ slot · 5k logic cells

5 V

Art and logos 2

Artwork Meme Chip

1 × ½ slot · 226 logic cells

placed 2 times

5 V Unsalicided poly resistors

WSLG

wafer.space Logo

1 × 1 slot · 14k logic cells

5 V

Test structures 2

Flip Chip pad test version 1

½ × ½ slot

RLCM: Test Passives For GF180MCUD

½ × 1 slot

chip-on-board

FPGA 1

FABulous FPGA

1 × 1 slot · 212k logic cells · 13 SRAM

chip-on-board

3.3 V

Security 1

Cloneless2

1 × 1 slot · 324k logic cells

5 V

Communications 1

Expresso Ethernet Chip: 100Mbps Ethernet switch + Heat death of the Universe Beacon - 0.5x0.5 version - Preferred version

½ × ½ slot · 9k logic cells

chip-on-board

5 V

Data and method

Everything on this page is measured from the public layout; the dates come from the published schedules.

Logic cells are standard cell instances, excluding fillers, taps, antenna diodes and tie cells.
Transistors are places where gate polysilicon crosses diffusion, not counting dummy fill.
Core area is each design's CORE_AREA, read from its own LibreLane config at the commit that was checked; where that could not be read, the project template's, 442 µm in from each edge of the die. Density inside the seal ring is over the whole die less its 26 µm seal ring: all the silicon a slot gives its designer, pad ring included.
Bond pads are the pad openings in the pad ring, or in a second ring of pads inside it for chip-on-board bonding; probe pads are the others, next to the blocks they test. Letters and logos on the pad layer are not pads.
Theoretical maximum tiles one cell at its placement boundary with no routing.
Densest mm² is the best 1 mm square anywhere in each die, sliding in 0.1 mm steps and avoiding SRAM.

The full written analysis is the density report. The measurements behind it:

Generated by ws-run-reports from layout/G802.oas (md5 57fa57f52eac82835a051f2a353e5a30).