Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

KianV uLinux SoC

518 · RISC-V and CPUs · 4 × 4 tiles

by Hirosh Dabui

Layout render of KianV uLinux SoC

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		19k (25% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (37% of buffer maximum)
Core covered by logic58%
Transistor density
transistors per mm²		296k average, 294k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A RISC-V ASIC that can boot μLinux.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1440 × 737 µm (1.061 mm²)
Macrott_um_kianV_rv32ima_uLinux_SoC
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles4 × 4 at column 0, row 1 of the tile grid
Mux address518
LanguageVerilog
Clock16 MHz
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors315,831
Logic cells20,266 + 42,242 filler and tap cells
Libraries 7t-5V (20k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

58%
40%
  • Logic cells 0.62 mm² (58%)
  • Filler and tap cells 0.43 mm² (40%)
  • Other 0.02 mm² (2%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nor2_17t-5V 2,3192-input NOR gate
dffq_47t-5V 2,146D flip-flop (1 bit storage, 4x drive)
nand2_17t-5V 2,0032-input NAND gate
aoi21_17t-5V 1,780AND-OR-Invert compound gate
buf_47t-5V 1,271Buffer (4x drive)
inv_17t-5V 1,214Inverter
oai211_17t-5V 1,111OR-AND-Invert compound gate
buf_27t-5V 622Buffer (2x drive)
aoi22_17t-5V 618AND-OR-Invert (2x2 inputs)
dffq_17t-5V 578D flip-flop (1 bit storage)

Logic density map

180 logic cells, 2,727 transistors 180 logic cells, 2,830 transistors 167 logic cells, 2,844 transistors 179 logic cells, 2,852 transistors 173 logic cells, 2,813 transistors 181 logic cells, 2,900 transistors 180 logic cells, 2,871 transistors 169 logic cells, 2,958 transistors 165 logic cells, 2,927 transistors 168 logic cells, 2,916 transistors 191 logic cells, 2,807 transistors 208 logic cells, 2,820 transistors 220 logic cells, 2,796 transistors 225 logic cells, 2,762 transistors 33 logic cells, 901 transistors 178 logic cells, 2,886 transistors 181 logic cells, 2,968 transistors 176 logic cells, 3,076 transistors 192 logic cells, 2,990 transistors 199 logic cells, 3,018 transistors 177 logic cells, 2,998 transistors 193 logic cells, 3,027 transistors 194 logic cells, 2,975 transistors 180 logic cells, 3,015 transistors 197 logic cells, 3,052 transistors 218 logic cells, 3,030 transistors 227 logic cells, 2,979 transistors 262 logic cells, 2,951 transistors 266 logic cells, 2,918 transistors 68 logic cells, 1,058 transistors 170 logic cells, 2,829 transistors 165 logic cells, 2,983 transistors 171 logic cells, 3,070 transistors 172 logic cells, 3,008 transistors 169 logic cells, 2,985 transistors 174 logic cells, 3,024 transistors 155 logic cells, 3,203 transistors 142 logic cells, 3,064 transistors 195 logic cells, 3,074 transistors 225 logic cells, 2,994 transistors 208 logic cells, 2,900 transistors 218 logic cells, 2,869 transistors 215 logic cells, 2,962 transistors 197 logic cells, 2,970 transistors 58 logic cells, 1,028 transistors 206 logic cells, 2,806 transistors 177 logic cells, 2,955 transistors 194 logic cells, 2,987 transistors 176 logic cells, 3,071 transistors 155 logic cells, 3,157 transistors 162 logic cells, 3,188 transistors 191 logic cells, 3,178 transistors 203 logic cells, 3,045 transistors 196 logic cells, 3,424 transistors 189 logic cells, 3,292 transistors 204 logic cells, 2,809 transistors 207 logic cells, 2,941 transistors 240 logic cells, 2,888 transistors 244 logic cells, 2,840 transistors 63 logic cells, 1,009 transistors 175 logic cells, 2,918 transistors 179 logic cells, 2,982 transistors 194 logic cells, 2,987 transistors 237 logic cells, 3,004 transistors 202 logic cells, 3,315 transistors 181 logic cells, 3,305 transistors 191 logic cells, 3,284 transistors 208 logic cells, 3,213 transistors 174 logic cells, 3,304 transistors 182 logic cells, 3,286 transistors 193 logic cells, 3,033 transistors 192 logic cells, 3,082 transistors 204 logic cells, 3,032 transistors 204 logic cells, 2,939 transistors 38 logic cells, 991 transistors 193 logic cells, 2,878 transistors 231 logic cells, 2,979 transistors 216 logic cells, 3,023 transistors 227 logic cells, 3,028 transistors 206 logic cells, 3,299 transistors 211 logic cells, 3,254 transistors 183 logic cells, 3,067 transistors 198 logic cells, 3,002 transistors 201 logic cells, 3,052 transistors 205 logic cells, 3,070 transistors 205 logic cells, 3,058 transistors 206 logic cells, 2,953 transistors 213 logic cells, 3,014 transistors 212 logic cells, 2,986 transistors 69 logic cells, 1,092 transistors 197 logic cells, 2,812 transistors 185 logic cells, 2,884 transistors 192 logic cells, 2,909 transistors 183 logic cells, 3,007 transistors 195 logic cells, 3,055 transistors 209 logic cells, 3,005 transistors 185 logic cells, 2,960 transistors 193 logic cells, 3,015 transistors 182 logic cells, 2,981 transistors 178 logic cells, 3,148 transistors 180 logic cells, 3,038 transistors 165 logic cells, 3,049 transistors 170 logic cells, 3,032 transistors 172 logic cells, 3,079 transistors 54 logic cells, 1,093 transistors 73 logic cells, 959 transistors 80 logic cells, 936 transistors 95 logic cells, 949 transistors 63 logic cells, 984 transistors 72 logic cells, 978 transistors 57 logic cells, 981 transistors 62 logic cells, 991 transistors 70 logic cells, 982 transistors 62 logic cells, 987 transistors 59 logic cells, 1,046 transistors 64 logic cells, 983 transistors 54 logic cells, 986 transistors 52 logic cells, 1,027 transistors 60 logic cells, 1,008 transistors 5 logic cells, 319 transistors Densest SRAM-free 0.1 mm square: 280 logic cells 18k 18k 17k 18k 17k 18k 18k 17k 16k 17k 19k 21k 22k 22k 18k 18k 18k 19k 20k 18k 19k 19k 18k 20k 22k 23k 26k 27k 17k 16k 17k 17k 17k 17k 15k 14k 19k 22k 21k 22k 21k 20k 21k 18k 19k 18k 15k 16k 19k 20k 20k 19k 20k 21k 24k 24k 17k 18k 19k 24k 20k 18k 19k 21k 17k 18k 19k 19k 20k 20k 19k 23k 22k 23k 21k 21k 18k 20k 20k 20k 20k 21k 21k 21k 20k 18k 19k 18k 19k 21k 18k 19k 18k 18k 18k 16k 17k 17k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

KianV RISC-V Linux SoC has been made on 10 shuttles since Nov 2023. Every version, oldest first, with this one in bold:

  1. Nov 2023 · Tiny Tapeout 5 KianV uLinux SoC — 8 × 2 tiles
  2. Apr 2024 · Tiny Tapeout 6 KianV uLinux SoC — 8 × 2 tiles
  3. Jun 2024 · Tiny Tapeout 7 KianV RISC-V RV32E Baremetal SoC — 3 × 2 tiles, RV32E bare-metal version
  4. Nov 2024 · Tiny Tapeout IHP 0.2 KianV RISC-V RV32E Baremetal SoC — 4 × 2 tiles, RV32E bare-metal version
  5. Nov 2025 · Tiny Tapeout GF 0.1 KianV uLinux SoC — in a shared block
  6. Nov 2025 · Tiny Tapeout GF 0.2 KianV uLinux SoC — 4 × 4 tiles
  7. Dec 2025 · wafer.space Run 1 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU — 1 × 1 slot, 5 V standard cells and SRAM
  8. Mar 2026 · Tiny Tapeout IHP 26a KianV SV32 TT Linux SoC — 8 × 4 tiles
  9. Jun 2026 · Tiny Tapeout GF 0.3 KianV uLinux SoC — 4 × 4 tiles
  10. Jul 2026 · wafer.space Run 2 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 — 1 × 1 slot, 3.3 V standard cells and SRAM

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

KianV RISC-V Linux SoC started as a few tiles on Tiny Tapeout 5 and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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