wafer.space Run 1

KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU

KIAN · RISC-V and CPUs · 1 × 1 slot

Layout render of KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		7k (12% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		5k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		13k (22% of buffer maximum)
Core covered by logic24%
Transistor density
transistors per mm²		189k average, 215k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

KianV SV32 (MMU) RV32IMA Zicntr Zicsr Zifencei SSTC Linux/XV6 SoC

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot E5 KIAN on the reticle
Bond pads74
Transistors2,442,357
Logic cells88,941 + 246,524 filler and tap cells
Libraries 9t-5V (89k)
SRAM21 macros, 86,016 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.5
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 2483ecb9cc00.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-16, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V9t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

15%
22%
25%
36%
  • Logic cells 3.11 mm² (15%)
  • SRAM 4.40 mm² (22%)
  • Filler and tap cells 4.95 mm² (25%)
  • Other 0.46 mm² (2%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_19t-5V 15,1042-input NAND gate
dffq_19t-5V 10,257D flip-flop (1 bit storage)
dlyc_19t-5V 9,027Delay buffer
clkinv_19t-5V 6,350Clock inverter
nor2_19t-5V 4,0412-input NOR gate
oai21_19t-5V 3,636OR-AND-Invert compound gate
buf_19t-5V 3,324Buffer
buf_49t-5V 3,091Buffer (4x drive)
aoi21_19t-5V 3,088AND-OR-Invert compound gate
buf_29t-5V 2,727Buffer (2x drive)

Logic density map

1,073 logic cells, 63,135 transistors, 8% SRAM 1,968 logic cells, 89,219 transistors, 34% SRAM 1,418 logic cells, 91,003 transistors, 41% SRAM 1,831 logic cells, 54,495 transistors, 1% SRAM 1,226 logic cells, 88,984 transistors, 39% SRAM 12,790 logic cells, 210,146 transistors 11,390 logic cells, 201,224 transistors, 4% SRAM 1,010 logic cells, 82,733 transistors, 38% SRAM 796 logic cells, 87,542 transistors, 43% SRAM 12,470 logic cells, 220,210 transistors 11,346 logic cells, 213,596 transistors, 4% SRAM 59 logic cells, 80,637 transistors, 42% SRAM 838 logic cells, 86,173 transistors, 43% SRAM 11,373 logic cells, 213,094 transistors 11,311 logic cells, 215,755 transistors, 4% SRAM 252 logic cells, 80,177 transistors, 41% SRAM 887 logic cells, 64,497 transistors, 17% SRAM 3,347 logic cells, 122,254 transistors, 34% SRAM 3,077 logic cells, 120,353 transistors, 34% SRAM 479 logic cells, 56,284 transistors, 20% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 Densest SRAM-free mm²: 12,888 logic cells 1k 2k 1k 2k 1k 13k 11k 1k 1k 12k 11k <1k 1k 11k 11k <1k 1k 3k 3k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (13k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram512x8m8wm121 4,096

KianV RISC-V Linux SoC has been made on 10 shuttles since Nov 2023. Every version, oldest first, with this one in bold:

  1. Nov 2023 · Tiny Tapeout 5 KianV uLinux SoC — 8 × 2 tiles
  2. Apr 2024 · Tiny Tapeout 6 KianV uLinux SoC — 8 × 2 tiles
  3. Jun 2024 · Tiny Tapeout 7 KianV RISC-V RV32E Baremetal SoC — 3 × 2 tiles, RV32E bare-metal version
  4. Nov 2024 · Tiny Tapeout IHP 0.2 KianV RISC-V RV32E Baremetal SoC — 4 × 2 tiles, RV32E bare-metal version
  5. Nov 2025 · Tiny Tapeout GF 0.1 KianV uLinux SoC — in a shared block
  6. Nov 2025 · Tiny Tapeout GF 0.2 KianV uLinux SoC — 4 × 4 tiles
  7. Dec 2025 · wafer.space Run 1 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU — 1 × 1 slot, 5 V standard cells and SRAM
  8. Mar 2026 · Tiny Tapeout IHP 26a KianV SV32 TT Linux SoC — 8 × 4 tiles
  9. Jun 2026 · Tiny Tapeout GF 0.3 KianV uLinux SoC — 4 × 4 tiles
  10. Jul 2026 · wafer.space Run 2 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 — 1 × 1 slot, 3.3 V standard cells and SRAM

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
wafer.space Run 1 · KIAN 1 × 19t-5V 5 V/6 V only 88,941 7k 13k 21 macros
wafer.space Run 2 · KIAN 1 × 1AS 7t-3.3V 3.3 V only 76,850 6k 15k 21 macros

From Tiny Tapeout tiles to a die of its own

KianV RISC-V Linux SoC began as tiles on Tiny Tapeout 5, and now has dies of its own on wafer.space Run 1 and wafer.space Run 2.

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. KIAN was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-16.

Every step, and the latest re-run
StepAccepted on
check 117, 2025-12-16, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 755, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCadvisory warningadvisory warning
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)22
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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