wafer.space Run 2

KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2

KIAN · RISC-V and CPUs · 1 × 1 slot

Layout render of KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		6k (8% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		4k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		15k (19% of buffer maximum)
Core covered by logic16%
Transistor density
transistors per mm²		182k average, 245k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

KianV SV32 MMU RV32IMA + Zicntr/Zicsr/Zifencei/Sstc Linux/Xv6 SoC, v3.3 standard cells

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot C5 KIAN on the reticle
Bond pads74
Transistors2,350,409
Logic cells76,850 + 445,794 filler and tap cells
Libraries AS 7t-3.3V (77k)
SRAM21 macros, 86,016 bits

Submission

LicenceMIT declared
Repository: Apache-2.0 in LICENSE, not the declared licence
Templatewafer-space/gf180mcu-project-template 1.5.8
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 0b383ba46257.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT f6eeac7dad08).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (5 V, 6 V) transistors
I/O librarygf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

11%
10%
42%
36%
  • Logic cells 2.13 mm² (11%)
  • SRAM 2.04 mm² (10%)
  • Filler and tap cells 8.44 mm² (42%)
  • Other 0.31 mm² (2%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dlybuff_2AS 7t-3.3V 20,354Delay buffer (2x drive)
dfxtp_2AS 7t-3.3V 10,286D flip-flop (1 bit storage, 2x drive)
buff_2AS 7t-3.3V 7,313Buffer (2x drive)
ao22_2AS 7t-3.3V 6,377AND-OR compound gate (2x2 inputs, 2x drive)
and2_2AS 7t-3.3V 5,1462-input AND gate (2x drive)
mux2_2AS 7t-3.3V 3,1132-input multiplexer (2x drive)
ao31_2AS 7t-3.3V 2,572AND-OR compound gate (3+1 inputs, 2x drive)
nor2_2AS 7t-3.3V 2,3112-input NOR gate (2x drive)
ao211_2AS 7t-3.3V 2,046AND-OR compound gate (2+1+1 inputs, 2x drive)
oai21_2AS 7t-3.3V 1,899OR-AND-Invert compound gate (2x drive)

Logic density map

34 logic cells, 37,753 transistors, 5% SRAM 2,655 logic cells, 109,416 transistors, 14% SRAM 1,585 logic cells, 107,709 transistors, 19% SRAM 10 logic cells, 22,388 transistors 94 logic cells, 90,942 transistors, 19% SRAM 12,205 logic cells, 215,139 transistors 8,948 logic cells, 174,883 transistors, 3% SRAM 20 logic cells, 84,566 transistors, 18% SRAM 2,056 logic cells, 116,144 transistors, 19% SRAM 13,391 logic cells, 223,737 transistors 13,854 logic cells, 236,868 transistors, 3% SRAM 11 logic cells, 84,151 transistors, 18% SRAM 499 logic cells, 95,987 transistors, 19% SRAM 13,431 logic cells, 221,926 transistors 6,298 logic cells, 148,041 transistors, 3% SRAM 20 logic cells, 84,504 transistors, 18% SRAM 35 logic cells, 54,811 transistors, 10% SRAM 1,645 logic cells, 103,899 transistors, 16% SRAM 41 logic cells, 90,476 transistors, 14% SRAM 18 logic cells, 46,223 transistors, 9% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 gf180mcu_ocd_ip_sram__sram512x8m8wm1 Densest SRAM-free mm²: 14,729 logic cells <1k 3k 2k <1k <1k 12k 9k <1k 2k 13k 14k <1k <1k 13k 6k <1k <1k 2k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (15k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram512x8m8wm121 4,096

KianV RISC-V Linux SoC has been made on 10 shuttles since Nov 2023. Every version, oldest first, with this one in bold:

  1. Nov 2023 · Tiny Tapeout 5 KianV uLinux SoC — 8 × 2 tiles
  2. Apr 2024 · Tiny Tapeout 6 KianV uLinux SoC — 8 × 2 tiles
  3. Jun 2024 · Tiny Tapeout 7 KianV RISC-V RV32E Baremetal SoC — 3 × 2 tiles, RV32E bare-metal version
  4. Nov 2024 · Tiny Tapeout IHP 0.2 KianV RISC-V RV32E Baremetal SoC — 4 × 2 tiles, RV32E bare-metal version
  5. Nov 2025 · Tiny Tapeout GF 0.1 KianV uLinux SoC — in a shared block
  6. Nov 2025 · Tiny Tapeout GF 0.2 KianV uLinux SoC — 4 × 4 tiles
  7. Dec 2025 · wafer.space Run 1 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU — 1 × 1 slot, 5 V standard cells and SRAM
  8. Mar 2026 · Tiny Tapeout IHP 26a KianV SV32 TT Linux SoC — 8 × 4 tiles
  9. Jun 2026 · Tiny Tapeout GF 0.3 KianV uLinux SoC — 4 × 4 tiles
  10. Jul 2026 · wafer.space Run 2 KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2 — 1 × 1 slot, 3.3 V standard cells and SRAM

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
wafer.space Run 1 · KIAN 1 × 19t-5V 5 V/6 V only 88,941 7k 13k 21 macros
wafer.space Run 2 · KIAN 1 × 1AS 7t-3.3V 3.3 V only 76,850 6k 15k 21 macros

From Tiny Tapeout tiles to a die of its own

KianV RISC-V Linux SoC began as tiles on Tiny Tapeout 5, and now has dies of its own on wafer.space Run 1 and wafer.space Run 2.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. KIAN was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.

Every step, and the latest re-run
StepAccepted on
check 524, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 726, 2026-08-02, retry, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

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