Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
ISHI-KAI's Multiple Projects Wafer for Wafer.Sapce GF180 Run 2.
| Die | 1.94 × 5.12 mm (9.9 mm²) |
|---|---|
| Core area | 4.47 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.57 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot G3 |
| Bond pads | 72 |
| Probe pads | 63 |
| Transistors | 44,494 |
| Logic cells | 0 + 63 filler and tap cells |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 1a0be37edb4b. |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 9,268 custom transistors |
|---|---|
| 5 V | 4,589 custom transistors |
| 6 V | 90 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 92 (13,262 µm², between Metal4 and Metal5) |
| MOS capacitors | 840
(35,280 µm²)
all in reused fill10_supplyVDD |
| High-resistance poly resistors | 33 (660 µm²) |
| Unsalicided poly resistors | 438 (32,465 µm²) |
| Diodes | 64 (307 µm²) |
| Deep N-well | 73 (19,484 µm²) |
| I/O library | gf180mcu_fd_io (785 cells) |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. ISHI was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.
Every step, and the latest re-run
| Step | Accepted on check 510, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 706, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.