Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
226 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Meme chip for marketing and swag
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.01 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 2 on the reticle, in slots E2, F2 |
| Bond pads | 72 |
| Transistors | 170,882 |
| Logic cells | 226 + 15,682 filler and tap cells |
| Libraries | 7t-5V (226) |
| SRAM | No SRAM |
Submission
| Licence | MIT declared
Repository: MIT in LICENSE — agrees |
|---|---|
| Template | egorxe/gf180mcu-caravel-template from its README |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit c11dda5b87b4. |
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| Unsalicided poly resistors | 192 (1,260 µm²) |
| I/O library | gf180mcu_fd_io (758 cells) |
Where the area went
How this design's area splits between filler and tap cells, other and pad ring.
- Filler and tap cells 0.68 mm² (7%)
- Other 4.33 mm² (44%)
- Pad ring 4.93 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buf_1 | 7t-5V | 89 | Buffer |
| dffq_1 | 7t-5V | 26 | D flip-flop (1 bit storage) |
| aoi21_1 | 7t-5V | 14 | AND-OR-Invert compound gate |
| nor2_1 | 7t-5V | 11 | 2-input NOR gate |
| oai21_1 | 7t-5V | 10 | OR-AND-Invert compound gate |
| clkbuf_1 | 7t-5V | 9 | Clock buffer |
| clkinv_1 | 7t-5V | 8 | Clock inverter |
| nor3_1 | 7t-5V | 8 | 3-input NOR gate |
| buf_2 | 7t-5V | 7 | Buffer (2x drive) |
| clkbuf_2 | 7t-5V | 7 | Clock buffer (2x drive) |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. MEME was accepted on this check, and has been checked again since with newer rules.
All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-14.
Every step, and the latest re-run
| Step | Accepted on check 516, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 712, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.