wafer.space Run 2

FABulous FPGA

MOLE · FPGA · 1 × 1 slot

Layout render of FABulous FPGA

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		16k (22% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		11k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		24k (32% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		317k average, 350k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

This is an improved version of my FABulous FPGA on wafer.space run 1. Notably, it uses 3.3V standard cells and SRAM macros, as well as 3.3V/5V compatible I/O cells.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot E5 MOLE on the reticle
Bond pads74
Transistors4,093,215
Logic cells211,813 + 341,915 filler and tap cells
Libraries AS 7t-3.3V (212k)
SRAM13 macros, 106,496 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.5.8
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 282dda832c62.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT f6eeac7dad08).
Chip-on-boardSelected at submission
PrecheckPassed the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells, ocd SRAM
Gate oxidesThin only (3.3 V) in the design itself
the pad ring adds thick-oxide (5 V, 6 V) transistors
I/O librarygf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

34%
10%
17%
36%
  • Logic cells 6.85 mm² (34%)
  • SRAM 2.02 mm² (10%)
  • Filler and tap cells 3.37 mm² (17%)
  • Other 0.68 mm² (3%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
buff_2AS 7t-3.3V 56,669Buffer (2x drive)
dlxtp_2AS 7t-3.3V 53,544Latch (level-sensitive, 2x drive)
mux4_2AS 7t-3.3V 27,4974-input multiplexer (2x drive)
mux2_2AS 7t-3.3V 20,9212-input multiplexer (2x drive)
inv_2AS 7t-3.3V 8,470Inverter (2x drive)
dlxfp_2AS 7t-3.3V 5,009Latch (level-sensitive, 2x drive)
dfxtp_2AS 7t-3.3V 3,290D flip-flop (1 bit storage, 2x drive)
or2_2AS 7t-3.3V 3,0072-input OR gate (2x drive)
nor2_2AS 7t-3.3V 3,0022-input NOR gate (2x drive)
aoi21_2AS 7t-3.3V 2,800AND-OR-Invert compound gate (2x drive)

Logic density map

4,446 logic cells, 74,730 transistors 9,400 logic cells, 148,339 transistors 8,367 logic cells, 134,957 transistors, 3% SRAM 7 logic cells, 94,686 transistors, 20% SRAM 11,211 logic cells, 176,399 transistors 22,831 logic cells, 351,837 transistors 20,305 logic cells, 318,560 transistors, 7% SRAM 10 logic cells, 181,506 transistors, 46% SRAM 10,439 logic cells, 163,794 transistors 23,266 logic cells, 351,123 transistors 20,892 logic cells, 318,808 transistors, 7% SRAM 7 logic cells, 200,945 transistors, 46% SRAM 10,293 logic cells, 164,141 transistors 23,145 logic cells, 352,383 transistors 20,522 logic cells, 318,490 transistors, 7% SRAM 10 logic cells, 195,587 transistors, 46% SRAM 4,409 logic cells, 79,373 transistors 11,681 logic cells, 186,103 transistors 10,568 logic cells, 170,365 transistors, 4% SRAM 4 logic cells, 110,243 transistors, 26% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 gf180mcu_ocd_ip_sram__sram1024x8m8wm1 Densest SRAM-free mm²: 24,122 logic cells 4k 9k 8k <1k 11k 23k 20k <1k 10k 23k 21k <1k 10k 23k 21k <1k 4k 12k 11k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (24k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_ocd_ip_sram__sram1024x8m8wm113 8,192

FABulous FPGA has been made on 9 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Google GFMPW-0 56C6 One-hot FABulous FPGA — Caravel chip, a one-hot FPGA built with the FABulous framework
  2. Dec 2025 · wafer.space Run 1 MOLE FABulous FPGA — 1 × 1 slot
  3. Mar 2026 · Tiny Tapeout IHP 26a Tiny FABulous FPGA — 8 × 4 tiles
  4. May 2026 · Tiny Tapeout SKY 26a Tiny FABulous FPGA — 8 × 4 tiles
  5. May 2026 · Tiny Tapeout SKY 26b Tiny FABulous FPGA — 8 × 4 tiles
  6. Jun 2026 · Tiny Tapeout GF 0.3 Tiny FABulous FPGA — 4 × 4 tiles Tiny FABulous FPGA (3.3V version) — 4 × 4 tiles, 3.3 V version
  7. Jul 2026 · wafer.space Run 2 MOLE FABulous FPGA — 1 × 1 slot
  8. Sep 2026 · Tiny Tapeout SKY 26c Tiny FABulous FPGA — 8 × 4 tiles
  9. Sep 2026 · Tiny Tapeout IHP 26b Tiny FABulous FPGA — 6 × 4 tiles

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 56C6 1 × 17t-5V 5 V/6 V only 32,037 4k 5k none
wafer.space Run 1 · MOLE 1 × 17t-5V 5 V/6 V only 203,757 16k 27k 6 macros
wafer.space Run 2 · MOLE 1 × 1AS 7t-3.3V 3.3 V only 211,813 16k 24k 13 macros

Parts of this design are on Tiny Tapeout chips too

Tiny Tapeout puts many small designs on one chip, so trying out a block costs a fraction of a whole die: a cheap way to test one piece of a bigger design before it goes on a die of its own.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. MOLE was accepted on this check, and has been checked again since with newer rules.

All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.

Every step, and the latest re-run
StepAccepted on
check 525, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1		Latest re-run
check 722, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.CheckPadMaskpassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

Reserve a slot
Start with Tiny Tapeout
← MEME Artwork Meme Chip All projects Naxos CoB NAX1 →