Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

Tiny FABulous FPGA (3.3V version)

359 · FPGA · 4 × 4 tiles

by Leo Moser

Layout render of Tiny FABulous FPGA (3.3V version)

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		24k (31% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		37k (49% of buffer maximum)
Core covered by logic60%
Transistor density
transistors per mm²		309k average, 429k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A tiny FABulous FPGA fabric, ready for use with Yosys and nextpnr.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1440 × 737 µm (1.061 mm²)
Macrott_um_fabulous_gf_0p3_3v3
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles4 × 4 at column 7, row 15 of the tile grid
Mux address359
LanguageVerilog
Transistors329,158
Logic cells25,184 + 31,777 filler and tap cells
Libraries AS 7t-3.3V (25k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 VAS 7t-3.3V standard cells
Gate oxidesThin only (3.3 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

60%
28%
12%
  • Logic cells 0.64 mm² (60%)
  • Filler and tap cells 0.29 mm² (28%)
  • Other 0.13 mm² (12%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
mux2_2AS 7t-3.3V 6,7962-input multiplexer (2x drive)
dlxfp_2AS 7t-3.3V 5,504Latch (level-sensitive, 2x drive)
buff_2AS 7t-3.3V 4,980Buffer (2x drive)
inv_2AS 7t-3.3V 1,128Inverter (2x drive)
nor2_2AS 7t-3.3V 8342-input NOR gate (2x drive)
nand2_2AS 7t-3.3V 6722-input NAND gate (2x drive)
ao31_2AS 7t-3.3V 578AND-OR compound gate (3+1 inputs, 2x drive)
nand2b_2AS 7t-3.3V 4872-input NAND, one input inverted (2x drive)
and2_2AS 7t-3.3V 4862-input AND gate (2x drive)
or2_2AS 7t-3.3V 4862-input OR gate (2x drive)

Logic density map

61 logic cells, 1,636 transistors 180 logic cells, 1,631 transistors 182 logic cells, 2,460 transistors 181 logic cells, 2,423 transistors 169 logic cells, 1,842 transistors 189 logic cells, 2,569 transistors 177 logic cells, 2,262 transistors 170 logic cells, 1,996 transistors 197 logic cells, 2,595 transistors 173 logic cells, 2,129 transistors 170 logic cells, 2,099 transistors 203 logic cells, 2,617 transistors 190 logic cells, 2,075 transistors 158 logic cells, 1,512 transistors 0 logic cells, 0 transistors 60 logic cells, 1,692 transistors 262 logic cells, 3,311 transistors 340 logic cells, 4,347 transistors 341 logic cells, 4,252 transistors 318 logic cells, 3,913 transistors 336 logic cells, 4,303 transistors 338 logic cells, 4,302 transistors 327 logic cells, 3,929 transistors 327 logic cells, 4,248 transistors 335 logic cells, 4,295 transistors 332 logic cells, 3,929 transistors 330 logic cells, 4,230 transistors 348 logic cells, 4,310 transistors 222 logic cells, 2,967 transistors 0 logic cells, 0 transistors 36 logic cells, 1,254 transistors 250 logic cells, 3,347 transistors 330 logic cells, 4,388 transistors 318 logic cells, 4,255 transistors 330 logic cells, 3,988 transistors 321 logic cells, 4,330 transistors 328 logic cells, 4,299 transistors 326 logic cells, 4,003 transistors 316 logic cells, 4,270 transistors 340 logic cells, 4,349 transistors 319 logic cells, 4,032 transistors 311 logic cells, 4,222 transistors 344 logic cells, 4,341 transistors 231 logic cells, 3,045 transistors 0 logic cells, 0 transistors 91 logic cells, 1,922 transistors 229 logic cells, 2,866 transistors 309 logic cells, 4,047 transistors 310 logic cells, 3,999 transistors 264 logic cells, 3,630 transistors 309 logic cells, 4,040 transistors 315 logic cells, 4,023 transistors 267 logic cells, 3,644 transistors 306 logic cells, 4,011 transistors 313 logic cells, 4,034 transistors 264 logic cells, 3,641 transistors 311 logic cells, 3,991 transistors 304 logic cells, 4,023 transistors 195 logic cells, 2,570 transistors 0 logic cells, 0 transistors 113 logic cells, 2,320 transistors 248 logic cells, 3,282 transistors 334 logic cells, 4,353 transistors 327 logic cells, 4,213 transistors 337 logic cells, 3,975 transistors 326 logic cells, 4,271 transistors 321 logic cells, 4,255 transistors 343 logic cells, 4,005 transistors 319 logic cells, 4,196 transistors 325 logic cells, 4,283 transistors 339 logic cells, 3,993 transistors 320 logic cells, 4,165 transistors 348 logic cells, 4,301 transistors 227 logic cells, 2,970 transistors 0 logic cells, 0 transistors 120 logic cells, 2,206 transistors 237 logic cells, 3,041 transistors 309 logic cells, 4,054 transistors 305 logic cells, 3,905 transistors 290 logic cells, 3,576 transistors 310 logic cells, 4,114 transistors 311 logic cells, 3,978 transistors 286 logic cells, 3,643 transistors 308 logic cells, 4,043 transistors 321 logic cells, 4,039 transistors 283 logic cells, 3,655 transistors 305 logic cells, 3,881 transistors 309 logic cells, 3,945 transistors 212 logic cells, 2,758 transistors 0 logic cells, 0 transistors 96 logic cells, 2,062 transistors 250 logic cells, 2,538 transistors 190 logic cells, 2,598 transistors 175 logic cells, 2,622 transistors 178 logic cells, 1,971 transistors 198 logic cells, 2,756 transistors 217 logic cells, 2,787 transistors 203 logic cells, 2,211 transistors 195 logic cells, 2,738 transistors 219 logic cells, 2,713 transistors 161 logic cells, 1,636 transistors 128 logic cells, 1,983 transistors 155 logic cells, 1,665 transistors 146 logic cells, 1,395 transistors 0 logic cells, 65 transistors 16 logic cells, 420 transistors 9 logic cells, 334 transistors 9 logic cells, 354 transistors 3 logic cells, 245 transistors 0 logic cells, 207 transistors 0 logic cells, 210 transistors 0 logic cells, 207 transistors 0 logic cells, 217 transistors 0 logic cells, 215 transistors 0 logic cells, 210 transistors 0 logic cells, 215 transistors 0 logic cells, 209 transistors 0 logic cells, 215 transistors 0 logic cells, 217 transistors 0 logic cells, 85 transistors Densest SRAM-free 0.1 mm square: 373 logic cells 6k 18k 18k 18k 17k 19k 18k 17k 20k 17k 17k 20k 19k 16k 6k 26k 34k 34k 32k 34k 34k 33k 33k 33k 33k 33k 35k 22k 4k 25k 33k 32k 33k 32k 33k 33k 32k 34k 32k 31k 34k 23k 9k 23k 31k 31k 26k 31k 31k 27k 31k 31k 26k 31k 30k 19k 11k 25k 33k 33k 34k 33k 32k 34k 32k 32k 34k 32k 35k 23k 12k 24k 31k 30k 29k 31k 31k 29k 31k 32k 28k 30k 31k 21k 10k 25k 19k 17k 18k 20k 22k 20k 19k 22k 16k 13k 15k 15k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (37k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

FABulous FPGA has been made on 9 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Google GFMPW-0 56C6 One-hot FABulous FPGA — Caravel chip, a one-hot FPGA built with the FABulous framework
  2. Dec 2025 · wafer.space Run 1 MOLE FABulous FPGA — 1 × 1 slot
  3. Mar 2026 · Tiny Tapeout IHP 26a Tiny FABulous FPGA — 8 × 4 tiles
  4. May 2026 · Tiny Tapeout SKY 26a Tiny FABulous FPGA — 8 × 4 tiles
  5. May 2026 · Tiny Tapeout SKY 26b Tiny FABulous FPGA — 8 × 4 tiles
  6. Jun 2026 · Tiny Tapeout GF 0.3 Tiny FABulous FPGA (3.3V version) — 4 × 4 tiles, 3.3 V version Tiny FABulous FPGA — 4 × 4 tiles
  7. Jul 2026 · wafer.space Run 2 MOLE FABulous FPGA — 1 × 1 slot
  8. Sep 2026 · Tiny Tapeout SKY 26c Tiny FABulous FPGA — 8 × 4 tiles
  9. Sep 2026 · Tiny Tapeout IHP 26b Tiny FABulous FPGA — 6 × 4 tiles

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

FABulous FPGA started as a few tiles on Tiny Tapeout IHP 26a and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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