Google GF180MCU open shuttle (GFMPW‑0)Run by Google and Efabless

40 public designs on one GF180MCU reticle

What was built

The run as a whole: what its designs add up to.

One of the free open-source GF180MCU shuttles that Google sponsored and Efabless ran. Each design sat in the user area of the Caravel harness, which took 55% of every die for its management SoC, pads and wiring. Its designs are measured here the same way as wafer.space's own runs, so you can compare them with a wafer.space die, where everything inside the pad ring is your design. The other Google shuttle measured here is MPW-18H1.

40

Public designs

filling all 40 slots

40

Open source

with a public repository

8.4M

Transistors

across the unique designs

192k

Logic cells

gates and flip-flops

256 bytes

SRAM

in foundry and custom macros

40

Whole dies

every slot a whole die

Private designs on the reticle are not in the public layout and are not counted. Designs placed more than once are counted once.

Make a chip of your own

These designs were made free on one of Google's shuttles. The same GF180MCU process is open to anyone on wafer.space: start small with a Tiny Tapeout tile, or go straight to a whole die on the next wafer.space run.

Make a whole chip of your own

Book a die to itself on wafer.space Run 3: orders close 9 December 2026.

Reserve a slot

Or start with a Tiny Tapeout tile

Tiny Tapeout GF 26c and 26d take projects until 7 December 2026, to be made on wafer.space Run 3.

Submit a project

Get a Tiny Tapeout chip

Every Tiny Tapeout chip comes on a board you can plug in, with all of its projects ready to try.

Buy a chip and board

The reticle

E8 · 8BB5 D8 · 8455 C8 · 9DDB B8 · 6E0D A8 · 5F3A E7 · F330 D7 · 8D82 C7 · A006 B7 · FF8E A7 · F0DD E6 · 45D6 D6 · 1E9A C6 · 472A B6 · 105A A6 · B22E E5 · 58D2 D5 · C301 C5 · 5FF2 B5 · 66AD A5 · EAD1 E4 · 6106 D4 · 7F0C C4 · 9C7C B4 · 4F9E A4 · BBE0 E3 · 679D D3 · C979 C3 · E91D B3 · 4515 A3 · B676 E2 · 14FB D2 · 6F7B C2 · 56C6 B2 · A3A3 A2 · EB3D E1 · 0AFF D1 · F4D8 C1 · 1F37 B1 · 0ABD A1 · 6079

Every design rendered from the layout at the same scale and placed where it sits on the 32 × 26 mm reticle. The slots are named as in the shuttle's own list: rows lettered from the top, columns numbered from the right. Point at a die to see its name, and select it for its details.Every die is listed further down.

Slots

How much of the reticle each design took: a 1 × 1 slot is a whole die of its own.

Total	40
1 × 1	40

Layout on GitHub

Shuttle status

How this run went, from the call for designs to the finished chips.

31 October 2022 Submissions open Google and Efabless open the first GF180MCU Open MPW shuttle, free to open source designs
5 December 2022, 11:59 PT Tapeout deadline Final deadline to submit projects; 86 projects submitted for 40 slots
21 December 2022 Final layouts Efabless commits the final layouts of the 40 selected projects, each inside the Caravel harness chip
3 January 2023 Layouts updated Last layout updates by Efabless (PR boundary layer removed)
31 March 2023 Assembly Packaging and assembly, on Efabless's schedule
2 June 2023 Delivery Chips and evaluation boards delivered to designers, on Efabless's schedule
Today, 24 October 2026

From the Efabless GFMPW-0 shuttle page (archived) and the shuttle repositories.

How people used their silicon

Where the area of 40 dies (805 mm² of silicon) actually went

40%

55%

Logic cells 1% — gates and flip-flops doing the design's actual work
Filler and tap cells 4% — inserted by the tools to keep rows continuous and wells tied
Other 40% — routing channels, analog and custom layout, power grid and empty space
Outside the user area 55% — the Caravel harness around the user's design: its management SoC, pads and wiring

What people built

The kinds of design on this run.

Other digital 25 RISC-V and CPUs 5 Retro computing 3 FPGA 2 Test structures 2 Multi-project die 1 Analog and mixed-signal 1 Accelerators 1

Standard cell libraries

The ready-made gate libraries the designs were built from: how many tracks tall each cell is, and the voltage it runs at.

Standard cell library	Logic cells	Share
7t-5V gf180mcu_fd_sc_mcu7t5v0	192k	100%

Area budget of every design

Each bar is one die, split the same way as above. Sorted by how much of the die is logic.

45D6 Ophelia eFPGA 56C6 One-hot FABulous FPGA C979 VerilogBoy 6079 Serv tri-core (GF180 MPW0 Serv) FF8E Hash accelerator with clock multiplexing B676 SPELL for GF180 66AD ALU (paper) 105A AS2650 F0DD Pyramiden Core (RV16U) 8BB5 PWM / Wishbone core E91D EduRISC16 0ABD VGA Clock for GF180

Show all 40 dies

9C7C GreenRio (GF version) 6E0D Synchronous modulator 1E9A HyperRAM controller 9DDB Asynchronous modulator 5F3A Clock divider 472A ChipFlow example SoC with 3.3V cells EB3D Jacaranda-8 8-bit CPU F4D8 OpenFASoC test structures in GF180MCU F330 16 x 4-bit dual port register file 679D Rift2Fake C301 8x8 Bit Pattern Player 0AFF PDM driver and dice A006 5-bit multiplier 7F0C Universal gates 1F37 Beep Boop Traffic Light Controller BBE0 posoco2000 6106 FiveGuys 8455 GF180 state machine B22E TestAsyncTrimux 5FF2 74181 ALU 4F9E MCU for solar power 8D82 XLS bit population count 6F7B Game of Life cell EAD1 Reversible programmable logic IC 58D2 TestFlipFlops 4515 Tiny user project: inverter 14FB SkullFET A3A3 Signed 8-bit multiplier

Which parts of the process were used

Transistor voltages and optional devices across the 40 designs

Transistor voltages

5 V 38

6 V 2

A design counts for a voltage when its standard cells, SRAM or its own transistors use it. 5 V and 6 V transistors share the thick gate oxide; a marker layer in the layout tells them apart.

Optional devices drawn by designers

Device	Designs	Which
eFuses	1	Ophelia eFPGA

Not drawn by any design: Native transistors, 10 V LDMOS, MIM capacitors, MOS capacitors, High-resistance poly resistors, Unsalicided poly resistors, Salicided poly resistors, Diffusion resistors, N-well resistors, Metal resistors, Diodes, Well diodes, Deep N-well, Bipolar transistors, Schottky diodes, Zener diodes, One-time programmable memory, Inductors.

Only devices outside standard cells, SRAM macros and I/O pads count, since every die has those. A single test structure counts the same as a large block.

Gate oxides

Transistors	Designs	Which
3.3 V and 5 V/6 V	0
3.3 V only	0
5 V/6 V only	39	39 designs VGA Clock for GF180, PDM driver and dice, AS2650, SkullFET, HyperRAM controller, Beep Boop Traffic Light Controller, Tiny user project: inverter, Ophelia eFPGA, ChipFlow example SoC with 3.3V cells, MCU for solar power, One-hot FABulous FPGA, TestFlipFlops, Clock divider, 74181 ALU, Serv tri-core (GF180 MPW0 Serv), FiveGuys, ALU (paper), Rift2Fake, Synchronous modulator, Game of Life cell, Universal gates, GF180 state machine, PWM / Wishbone core, XLS bit population count, GreenRio (GF version), Asynchronous modulator, 5-bit multiplier, TestAsyncTrimux, SPELL for GF180, posoco2000, 8x8 Bit Pattern Player, VerilogBoy, EduRISC16, Reversible programmable logic IC, Jacaranda-8 8-bit CPU, Pyramiden Core (RV16U), 16 x 4-bit dual port register file, OpenFASoC test structures in GF180MCU, Hash accelerator with clock multiplexing

3.3 V transistors have the thin gate oxide; 5 V and 6 V ones share the thick one. No transistors of their own: Signed 8-bit multiplier.

What fits on 1 mm² of GF180MCU silicon?

Theoretical maximum against what designers achieved

The maximum packs one cell type edge to edge with no room for wiring. Real designs need the wiring. Each box gives the most of a cell that fits with any GF180MCU library, then with the libraries this run used.

~114k

Inverters per mm²

GF180MCU maximum,
with AS 7t-3.3V inv_2

With this run's libraries:

7t-5V: 114k inv_1

~91k

NAND gates per mm²

GF180MCU maximum,
with 7t-5V nand2_1

With this run's libraries:

7t-5V: 91k nand2_1

~76k

Buffers per mm²

GF180MCU maximum,
with AS 7t-3.3V buff_2

With this run's libraries:

7t-5V: 76k buf_1

~17k

Flip-flops per mm²

GF180MCU maximum,
with AS 7t-3.3V dfxtp_2

With this run's libraries:

7t-5V: 16k dffq_1

7k

Best core average

logic cells/mm² of core — 9% of the buffer maximum

Ophelia eFPGA

19k

Densest mm²

logic cells — 25% of the buffer maximum

Ophelia eFPGA

<1k

Typical die

median logic cells/mm² of core across 16 digital dies (1,000 or more logic cells)

1% of the core covered by logic cells

Percentages compare with the buffer maximum for each design's own library: buffers are among the smallest and most common logic cells, so a design made only of buffers, packed edge to edge with no wiring, would reach 100%.

Sizing your own design

What each slot size held on this run, and what it would hold at its densities

				Logic cells in its digital designs1,000 or more logic cells		Logic cells at this run's density			Theoretical maximum, 7t-5V cells
Slot	Die	Core area	Designs	Most	Median	Typical<1k / mm²	Best7k / mm²	Densest19k / mm²	NAND gatesnand2_1	Flip-flopsdffq_1
1 × 1	3.93 × 5.12 mm	9.0 mm²	40	65k	4k	4k	65k	169k	820k	141k

Swipe the table sideways for more columns.

Core area is the area of each die's user_project_wrapper cell. "Typical" and "best" multiply the core area by this run's median and best core densities, and "densest" by the densest 1 mm² any design on this run reached; SRAM and analog blocks take their area out of that. The theoretical maxima fill the core with nothing but that one cell of 7t-5V, the library most used on this run, edge to edge with no routing.

Pick the slot size your design needs on wafer.space Run 3: orders close 9 December 2026.

Logic density of every digital design

A digital die here is one with 1,000 or more logic cells. Solid bar: average over the core. Outlined bar: the densest mm² outside SRAM (a dash where memory covers most of the design). The scale ends at the buffer theoretical maximum (76k cells/mm²). The numbers are core / densest, in logic cells per mm².

45D6 Ophelia eFPGA 7k / 19k 56C6 One-hot FABulous FPGA 4k / 5k C979 VerilogBoy 3k / 18k 6079 Serv tri-core (GF180 MPW0 Serv) 2k / 12k FF8E Hash accelerator with clock multiplexing 1k / 8k B676 SPELL for GF180 1k / 6k 66AD ALU (paper) 1k / 6k 105A AS2650 1k / 5k F0DD Pyramiden Core (RV16U) <1k / 4k 8BB5 PWM / Wishbone core <1k / 2k E91D EduRISC16 <1k / 2k 6E0D Synchronous modulator <1k / 2k

Show all 16 digital dies

9DDB Asynchronous modulator <1k / 1k 0ABD VGA Clock for GF180 <1k / 1k 9C7C GreenRio (GF version) <1k / 1k 1E9A HyperRAM controller <1k / 1k

Every digital die's densities as a table

Design	Slot	Library	Logic cells	Inside core per mm²	Densest mm² per mm²	Core covered	Core mm²
Ophelia eFPGA 45D6	1 × 1	7t-5V	64,755	7,197	18,753	17%	9.00
One-hot FABulous FPGA 56C6	1 × 1	7t-5V	32,037	3,561	5,395	11%	9.00
VerilogBoy C979	1 × 1	7t-5V	27,097	3,012	18,124	8%	9.00
Serv tri-core (GF180 MPW0 Serv) 6079	1 × 1	7t-5V	17,345	1,928	12,266	6%	9.00
Hash accelerator with clock multiplexing FF8E	1 × 1	7t-5V	12,962	1,441	8,276	5%	9.00
SPELL for GF180 B676	1 × 1	7t-5V	6,463	718	6,463	2%	9.00
ALU (paper) 66AD	1 × 1	7t-5V	5,960	662	5,960	1%	9.00
AS2650 105A	1 × 1	7t-5V	4,846	539	4,846	1%	9.00
Pyramiden Core (RV16U) F0DD	1 × 1	7t-5V	3,874	431	3,874	1%	9.00
PWM / Wishbone core 8BB5	1 × 1	7t-5V	2,471	275	2,471	1%	9.00
EduRISC16 E91D	1 × 1	7t-5V	2,034	226	2,004	<1%	9.00
Synchronous modulator 6E0D	1 × 1	7t-5V	1,558	173	1,558	<1%	9.00
Asynchronous modulator 9DDB	1 × 1	7t-5V	1,470	163	1,470	<1%	9.00
VGA Clock for GF180 0ABD	1 × 1	7t-5V	1,319	147	1,319	<1%	9.00
GreenRio (GF version) 9C7C	1 × 1	7t-5V	1,319	147	1,319	<1%	9.00
HyperRAM controller 1E9A	1 × 1	7t-5V	1,155	128	1,155	<1%	9.00

The projects

Every design on this run: an index, then grouped by what it does. Select one for its layout, its measurements and any die photographs.

Design index

All 40 public designs by their code, with the slot each took and how much logic it packs.

Code	Design	Slot	What it is	Logic cells	Cells per mm²
0ABD	VGA Clock for GF180	1 × 1	Retro computing	1,319	<1k
0AFF	PDM driver and dice	1 × 1	Other digital	151	<1k
105A	AS2650	1 × 1	Retro computing	4,846	1k
14FB	SkullFET	1 × 1	Analog and mixed-signal	0
1E9A	HyperRAM controller	1 × 1	Other digital	1,155	<1k
1F37	Beep Boop Traffic Light Controller	1 × 1	Other digital	154	<1k
4515	Tiny user project: inverter	1 × 1	Test structures	24	<1k
45D6	Ophelia eFPGA	1 × 1	FPGA	64,755	7k
472A	ChipFlow example SoC with 3.3V cells	1 × 1	RISC-V and CPUs	727	<1k
4F9E	MCU for solar power	1 × 1	Other digital	43	<1k
56C6	One-hot FABulous FPGA	1 × 1	FPGA	32,037	4k
58D2	TestFlipFlops	1 × 1	Other digital	28	<1k
5F3A	Clock divider	1 × 1	Other digital	605	<1k
5FF2	74181 ALU	1 × 1	Other digital	77	<1k
6079	Serv tri-core (GF180 MPW0 Serv)	1 × 1	RISC-V and CPUs	17,345	2k
6106	FiveGuys	1 × 1	Other digital	105	<1k
66AD	ALU (paper)	1 × 1	Other digital	5,960	1k
679D	Rift2Fake	1 × 1	Other digital	308	<1k
6E0D	Synchronous modulator	1 × 1	Other digital	1,558	<1k
6F7B	Game of Life cell	1 × 1	Other digital	43	<1k
7F0C	Universal gates	1 × 1	Other digital	182	<1k
8455	GF180 state machine	1 × 1	Other digital	88	<1k
8BB5	PWM / Wishbone core	1 × 1	Other digital	2,471	<1k
8D82	XLS bit population count	1 × 1	Multi-project die	48	<1k
9C7C	GreenRio (GF version)	1 × 1	Other digital	1,319	<1k
9DDB	Asynchronous modulator	1 × 1	Other digital	1,470	<1k
A006	5-bit multiplier	1 × 1	Other digital	163	<1k
A3A3	Signed 8-bit multiplier	1 × 1	Other digital	0
B22E	TestAsyncTrimux	1 × 1	Other digital	89	<1k
B676	SPELL for GF180	1 × 1	Other digital	6,463	1k
BBE0	posoco2000	1 × 1	Other digital	115	<1k
C301	8x8 Bit Pattern Player	1 × 1	Other digital	201	<1k
C979	VerilogBoy	1 × 1	RISC-V and CPUs	27,097	3k
E91D	EduRISC16	1 × 1	RISC-V and CPUs	2,034	<1k
EAD1	Reversible programmable logic IC	1 × 1	Other digital	44	<1k
EB3D	Jacaranda-8 8-bit CPU	1 × 1	Retro computing	727	<1k
F0DD	Pyramiden Core (RV16U)	1 × 1	RISC-V and CPUs	3,874	<1k
F330	16 x 4-bit dual port register file	1 × 1	Other digital	388	<1k
F4D8	OpenFASoC test structures in GF180MCU	1 × 1	Test structures	727	<1k
FF8E	Hash accelerator with clock multiplexing	1 × 1	Accelerators	12,962	1k

Show all 40 designsShow the first 16 only

Swipe the table sideways for more columns.

Designs that grew

These designs have been made more than once: first as a Tiny Tapeout tile or on a Google shuttle, then on wafer.space, or improved and made again on a later run. Start small, then come back bigger. The ringed marker is this run.

FABulous FPGA 56C6

Avalon Semiconductors' retro-computing family 105A

SERV multi-core RISC-V SoC 6079

Tiny Tapeout tile Google shuttle wafer.space die this run
Each marker is one version of the design: hover over it or focus it for details, and select it to open its page. On a phone, the table below lists every one.

As a table

Design	Made on	When	Version	Size
FABulous FPGA	Google GFMPW-0	Dec 2022	56C6 One-hot FABulous FPGA	Caravel chip
	wafer.space Run 1	Dec 2025	MOLE FABulous FPGA	1 × 1 slot
	Tiny Tapeout IHP 26a	Mar 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout SKY 26a	May 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout SKY 26b	May 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout GF 0.3	Jun 2026	Tiny FABulous FPGA; Tiny FABulous FPGA (3.3V version)	4 × 4 tiles
	wafer.space Run 2	Jul 2026	MOLE FABulous FPGA	1 × 1 slot
	Tiny Tapeout SKY 26c	Sep 2026	Tiny FABulous FPGA	8 × 4 tiles
	Tiny Tapeout IHP 26b	Sep 2026	Tiny FABulous FPGA	6 × 4 tiles
Avalon Semiconductors' retro-computing family	Tiny Tapeout 2	Dec 2022	Avalon Semiconductors '5401' 4-bit Microprocessor; Avalon Semiconductors 'TBB1143' Programmable Sound Generator	1 × 1 tile
	Google GFMPW-0	Dec 2022	105A AS2650	Caravel chip
	Tiny Tapeout 3	Apr 2023	Avalon Semiconductors '5401' 4-bit Microprocessor; Avalon Semiconductors 'TBB1143' Programmable Sound Generator	1 × 1 tile
	wafer.space Run 1	Dec 2025	AS03 WS-Multi	1 × 1 slot
	wafer.space Run 2	Jul 2026	AS04 Multi-Project die using 3.3V SCL	1 × 1 slot
SERV multi-core RISC-V SoC	Tiny Tapeout 2	Dec 2022	serv - Serial RISC-V CPU	1 × 1 tile
	Google GFMPW-0	Dec 2022	6079 Serv tri-core (GF180 MPW0 Serv)	Caravel chip
	Tiny Tapeout 3	Apr 2023	serv - Serial RISC-V CPU	1 × 1 tile
	wafer.space Run 1	Dec 2025	GD02 Racquet Half r1p0 (1/2 slot); GD03 Racquet r2p0 - 23 core SoC; GD04 Racquet Wide 1x0.5	GD02 ½ × 1 slot, GD03 1 × 1 slot, GD04 1 × ½ slot
	wafer.space Run 2	Jul 2026	GD04 Racquet Wide 1x0.5	1 × ½ slot

Other digital 25

PDM driver and dice

1 × 1 slot · 151 logic cells

5 V

HyperRAM controller

1 × 1 slot · 1k logic cells

5 V

Beep Boop Traffic Light Controller

1 × 1 slot · 154 logic cells

5 V

MCU for solar power

1 × 1 slot · 43 logic cells

5 V

TestFlipFlops

1 × 1 slot · 28 logic cells

5 V

Clock divider

1 × 1 slot · 605 logic cells

5 V

74181 ALU

1 × 1 slot · 77 logic cells

5 V

FiveGuys

1 × 1 slot · 105 logic cells

5 V

ALU (paper)

1 × 1 slot · 6k logic cells

5 V

Rift2Fake

1 × 1 slot · 308 logic cells

5 V

Synchronous modulator

1 × 1 slot · 2k logic cells

5 V

Game of Life cell

1 × 1 slot · 43 logic cells

5 V

Show all 25 in Other digital

Universal gates

1 × 1 slot · 182 logic cells

5 V

GF180 state machine

1 × 1 slot · 88 logic cells

5 V

PWM / Wishbone core

1 × 1 slot · 2k logic cells

5 V

GreenRio (GF version)

1 × 1 slot · 1k logic cells

5 V

Asynchronous modulator

1 × 1 slot · 1k logic cells

5 V

5-bit multiplier

1 × 1 slot · 163 logic cells

5 V

Signed 8-bit multiplier

1 × 1 slot · 16k transistors

TestAsyncTrimux

1 × 1 slot · 89 logic cells

5 V

SPELL for GF180

1 × 1 slot · 6k logic cells

5 V

posoco2000

1 × 1 slot · 115 logic cells

5 V

8x8 Bit Pattern Player

1 × 1 slot · 201 logic cells

5 V

Reversible programmable logic IC

1 × 1 slot · 44 logic cells

5 V

16 x 4-bit dual port register file

1 × 1 slot · 388 logic cells

5 V

RISC-V and CPUs 5

ChipFlow example SoC with 3.3V cells

1 × 1 slot · 727 logic cells

5 V

Serv tri-core (GF180 MPW0 Serv)

1 × 1 slot · 17k logic cells · 1 SRAM

5 V

VerilogBoy

1 × 1 slot · 27k logic cells

5 V

EduRISC16

1 × 1 slot · 2k logic cells

5 V

Pyramiden Core (RV16U)

1 × 1 slot · 4k logic cells

5 V

Retro computing 3

VGA Clock for GF180

1 × 1 slot · 1k logic cells

5 V

AS2650

1 × 1 slot · 5k logic cells

5 V

Jacaranda-8 8-bit CPU

1 × 1 slot · 727 logic cells

5 V

FPGA 2

Ophelia eFPGA

1 × 1 slot · 65k logic cells

photo

5 V · 6 V eFuses

One-hot FABulous FPGA

1 × 1 slot · 32k logic cells

5 V

Test structures 2

Tiny user project: inverter

1 × 1 slot · 24 logic cells

5 V

OpenFASoC test structures in GF180MCU

1 × 1 slot · 727 logic cells

photo

5 V

Multi-project die 1

XLS bit population count

1 × 1 slot · 48 logic cells

5 V

Analog and mixed-signal 1

SkullFET

1 × 1 slot · 6 transistors

6 V

Accelerators 1

Hash accelerator with clock multiplexing

1 × 1 slot · 13k logic cells

5 V

The real silicon

45D6

F4D8

Data and method

Everything on this page is measured from the public layout; the dates come from the Efabless GFMPW-0 shuttle page (archived) and the shuttle repositories.

Logic cells are standard cell instances, excluding fillers, taps, antenna diodes and tie cells.
Transistors are places where gate polysilicon crosses diffusion, not counting dummy fill.
Core area is the area of each die's user_project_wrapper cell.
Excluded from the measurements: pad ring (gf180mcu_*_io__*); caravel harness (caravel_core, caravel_power_routing, chip_io, caravel_logo, caravel_motto, copyright_block, open_source, user_id_textblock); seal ring (sealring). Die sizes are measured on the whole die, and bond pads on the whole die apart from its seal ring.
Bond pads are the pad openings in the pad ring, or in a second ring of pads inside it for chip-on-board bonding; probe pads are the others, next to the blocks they test. Letters and logos on the pad layer are not pads.
Theoretical maximum tiles one cell at its placement boundary with no routing.
Densest mm² is the best 1 mm square anywhere in each die, sliding in 0.1 mm steps and avoiding SRAM.

The full written analysis is the density report. The measurements behind it:

Generated by ws-run-reports from layout/GFMPW0.oas (md5 366739415ab37e49a4330761db15c940).