Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

Clock divider

5F3A · Other digital · 1 × 1 slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

605 logic cells: too few for density figures, which are given for designs of 1,000 or more.

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Clock divider by 2 to 1024, to test the GF180 technology at CINVESTAV Guadalajara.

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot A8 5F3A on the reticle
Bond pads63
Transistors19,638
Logic cells605 + 4,237 filler and tap cells
Libraries 7t-5V (605)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and outside the user area.

44%
55%
  • Logic cells 0.03 mm² (<1%)
  • Filler and tap cells 0.05 mm² (<1%)
  • Other 8.92 mm² (44%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 290D flip-flop (1 bit storage)
clkbuf_167t-5V 55Clock buffer (16x drive)
nor2_17t-5V 462-input NOR gate
nor4_17t-5V 424-input NOR gate
nor3_17t-5V 253-input NOR gate
and2_17t-5V 182-input AND gate
aoi21_17t-5V 18AND-OR-Invert compound gate
clkbuf_17t-5V 17Clock buffer
clkbuf_37t-5V 10Clock buffer (3x drive)
xnor2_17t-5V 102-input XNOR gate

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.