Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

Hash accelerator with clock multiplexing

FF8E · Accelerators · 1 × 1 slot

Layout render of Hash accelerator with clock multiplexing

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		1k (2% of buffer maximum)
Densest mm²
logic cells per mm²		8k (11% of buffer maximum)
Core covered by logic5%
Transistor density
transistors per mm²		217k average, 250k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot B7 FF8E on the reticle
Bond pads63
Transistors1,951,950
Logic cells12,962 + 248,775 filler and tap cells
Libraries 7t-5V (13k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and outside the user area.

41%
55%
  • Logic cells 0.41 mm² (2%)
  • Filler and tap cells 8.31 mm² (41%)
  • Other 0.27 mm² (1%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffrnq_17t-5V 1,751D flip-flop with reset
oai21_17t-5V 1,316OR-AND-Invert compound gate
nand2_17t-5V 1,3072-input NAND gate
nor2_17t-5V 1,0382-input NOR gate
mux2_27t-5V 7882-input multiplexer (2x drive)
clkbuf_17t-5V 773Clock buffer
buf_27t-5V 572Buffer (2x drive)
aoi22_17t-5V 556AND-OR-Invert (2x2 inputs)
aoi21_17t-5V 547AND-OR-Invert compound gate
clkbuf_167t-5V 463Clock buffer (16x drive)

Logic density map

0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 1,166 logic cells, 42,392 transistors 1,713 logic cells, 79,239 transistors 147 logic cells, 72,038 transistors 0 logic cells, 31,340 transistors 2,648 logic cells, 120,856 transistors 6,279 logic cells, 240,044 transistors 1,008 logic cells, 222,609 transistors 1 logic cells, 96,557 transistors 0 logic cells, 111,435 transistors 0 logic cells, 218,025 transistors 0 logic cells, 218,280 transistors 0 logic cells, 96,370 transistors 0 logic cells, 69,679 transistors 0 logic cells, 136,333 transistors 0 logic cells, 136,492 transistors 0 logic cells, 60,261 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors Densest SRAM-free mm²: 8,276 logic cells 0 0 0 0 1k 2k <1k 0 3k 6k 1k <1k 0 0 0 0 0 0 0 0

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (8k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

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