Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

AS2650

105A · Retro computing · 1 × 1 slot

Layout render of AS2650

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		1k (1% of buffer maximum)
Densest mm²
logic cells per mm²		5k (6% of buffer maximum)
Core covered by logic1%
Transistor density
transistors per mm²		12k average, 107k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Avalon Semiconductors AS2650: partial implementation of the Signetics 2650 8-bit CPU architecture from 1975.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot B6 105A on the reticle
Bond pads63
Transistors106,901
Logic cells4,846 + 33,191 filler and tap cells
Libraries 7t-5V (5k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and outside the user area.

42%
55%
  • Logic cells 0.11 mm² (1%)
  • Filler and tap cells 0.40 mm² (2%)
  • Other 8.49 mm² (42%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
clkbuf_17t-5V 751Clock buffer
nand2_17t-5V 6432-input NAND gate
nor2_17t-5V 4192-input NOR gate
buf_17t-5V 365Buffer
aoi21_17t-5V 299AND-OR-Invert compound gate
dffq_17t-5V 283D flip-flop (1 bit storage)
oai21_17t-5V 274OR-AND-Invert compound gate
xor2_17t-5V 1642-input XOR gate
oai211_17t-5V 158OR-AND-Invert compound gate
nand3_17t-5V 1383-input NAND gate

Logic density map

0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 1,811 logic cells, 41,030 transistors 3,035 logic cells, 65,871 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors Densest SRAM-free mm²: 4,846 logic cells 0 0 0 0 0 0 0 0 0 0 0 0 0 2k 3k 0 0 0 0 0

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (5k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Avalon Semiconductors' retro-computing family has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Tiny Tapeout 2 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
  2. Dec 2022 · Google GFMPW-0 105A AS2650 — Caravel chip, a Signetics 2650 8-bit CPU replica
  3. Apr 2023 · Tiny Tapeout 3 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
  4. Dec 2025 · wafer.space Run 1 AS03 WS-Multi — 1 × 1 slot, a multi-project die: 6502 and SID replicas, an RV32IMA core, a DRAM controller and more
  5. Jul 2026 · wafer.space Run 2 AS04 Multi-Project die using 3.3V SCL — 1 × 1 slot, the multi-project die again, on 3.3 V standard cells

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 105A 1 × 17t-5V 5 V/6 V only 4,846 1k 5k none
wafer.space Run 1 · AS03 1 × 1mixed 5 V/6 V only 86,629 7k 21k none
wafer.space Run 2 · AS04 1 × 1AS 7t-3.3V 3.3 V only 87,322 7k 19k none

From Tiny Tapeout tiles to a die of its own

Avalon Semiconductors' retro-computing family was tried on Tiny Tapeout 2, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

Reserve a slot
Start with Tiny Tapeout
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