Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 7k
(9% of buffer maximum) over the 12.92 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 4k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 19k (25% of buffer maximum) |
| Core covered by logic | 18% |
| Transistor density transistors per mm² | 136k average, 263k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Contains:
- 6502/6510/PLA replicas
- SID replicas
- rv32ima_zicsr_smnmi core
- Retro DRAM controller
- GPIO chip
- NTSC Test signal generator
- FM Synth
- Digital-to-Analog converters
- Two layouts generated using [FeatherLane](https://codeberg.org/TholinVali/FeatherLane)
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.92 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot F5 |
| Bond pads | 74 |
| Transistors | 1,761,176 |
| Logic cells | 87,322 + 494,369 filler and tap cells |
| Libraries | AS 7t-3.3V (87k) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.5.7 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit a8d75525ecc6.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT d658698bd8bc). |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-14, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | AS 7t-3.3V standard cells, 192 custom transistors |
|---|---|
| Gate oxides | Thin only (3.3 V) in the design itself the pad ring adds thick-oxide (5 V, 6 V) transistors |
| MIM capacitors | 1 (900 µm², between Metal4 and Metal5) |
| MOS capacitors | 144
(32,400 µm²)
all in reused apad |
| High-resistance poly resistors | 126 (2,842 µm²) |
| Unsalicided poly resistors | 2 (1,800 µm²) |
| Salicided poly resistors | 2 (1,800 µm²) |
| Diffusion resistors | 2 (13,728 µm²) |
| Diodes | 48
(6,169 µm²)
all in reused apad |
| I/O library | gf180mcu_ocd_io (1136 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 2.31 mm² (11%)
- Filler and tap cells 7.58 mm² (38%)
- Other 3.02 mm² (15%)
- Pad ring 7.20 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| buff_2 | AS 7t-3.3V | 11,540 | Buffer (2x drive) |
| mux2_2 | AS 7t-3.3V | 10,377 | 2-input multiplexer (2x drive) |
| and2_2 | AS 7t-3.3V | 6,981 | 2-input AND gate (2x drive) |
| dfxtp_2 | AS 7t-3.3V | 4,901 | D flip-flop (1 bit storage, 2x drive) |
| ao22_2 | AS 7t-3.3V | 4,472 | AND-OR compound gate (2x2 inputs, 2x drive) |
| xnor2_2 | AS 7t-3.3V | 4,381 | 2-input XNOR gate (2x drive) |
| nand2_2 | AS 7t-3.3V | 3,957 | 2-input NAND gate (2x drive) |
| nor2_2 | AS 7t-3.3V | 3,106 | 2-input NOR gate (2x drive) |
| dlybuff_2 | AS 7t-3.3V | 2,734 | Delay buffer (2x drive) |
| ao21_2 | AS 7t-3.3V | 2,502 | AND-OR compound gate (2x drive) |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (19k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
How this design grew
Avalon Semiconductors' retro-computing family has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:
- Dec 2022 · Tiny Tapeout 2 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
- Dec 2022 · Google GFMPW-0 105A AS2650 — Caravel chip, a Signetics 2650 8-bit CPU replica
- Apr 2023 · Tiny Tapeout 3 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
- Dec 2025 · wafer.space Run 1 AS03 WS-Multi — 1 × 1 slot, a multi-project die: 6502 and SID replicas, an RV32IMA core, a DRAM controller and more
- Jul 2026 · wafer.space Run 2 AS04 Multi-Project die using 3.3V SCL — 1 × 1 slot, the multi-project die again, on 3.3 V standard cells
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| Google GFMPW-0 · 105A | 1 × 1 | 7t-5V | 5 V/6 V only | 4,846 | 1k | 5k | none |
| wafer.space Run 1 · AS03 | 1 × 1 | mixed | 5 V/6 V only | 86,629 | 7k | 21k | none |
| wafer.space Run 2 · AS04 | 1 × 1 | AS 7t-3.3V | 3.3 V only | 87,322 | 7k | 19k | none |
From Tiny Tapeout tiles to a die of its own
Avalon Semiconductors' retro-computing family was tried on Tiny Tapeout 2 and a Google shuttle, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. AS04 was accepted on this check, and has been checked again since with newer rules.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-14.
Every step, and the latest re-run
| Step | Accepted on check 528, 2026-07-14, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 728, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.CheckPadMask | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.