Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 6k
(8% of buffer maximum) over the 5.02 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 3k
over all 9.61 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 19k (24% of buffer maximum) |
| Core covered by logic | 19% |
| Transistor density transistors per mm² | 249k average, 285k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
LibreLane digital project implementing Anton Maurovic's (algofoogle's) raybox-zero "3D" ray caster demo with SPI interface for "game like" control by a host PC or MCU, optional texture-map QSPI ROM interface, and Tiny VGA compatible digital RGB222 VGA output.
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.02 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 2 on the reticle, in slots B2, C2 |
| Bond pads | 72 |
| Transistors | 1,248,073 |
| Logic cells | 31,608 + 122,990 filler and tap cells |
| Libraries | 7t-5V (32k) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.5.7 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit f5bbcef7564e.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_COMMIT d658698bd8bc). |
| Chip-on-board | Selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (758 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 0.94 mm² (9%)
- Filler and tap cells 4.07 mm² (41%)
- Other 0.01 mm² (<1%)
- Pad ring 4.92 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| dlyb_1 | 7t-5V | 11,385 | Delay buffer |
| nand2_1 | 7t-5V | 1,624 | 2-input NAND gate |
| nor2_1 | 7t-5V | 1,610 | 2-input NOR gate |
| dffq_1 | 7t-5V | 1,378 | D flip-flop (1 bit storage) |
| oai21_1 | 7t-5V | 1,343 | OR-AND-Invert compound gate |
| aoi21_1 | 7t-5V | 1,305 | AND-OR-Invert compound gate |
| nand3_1 | 7t-5V | 904 | 3-input NAND gate |
| buf_4 | 7t-5V | 855 | Buffer (4x drive) |
| nand4_1 | 7t-5V | 722 | 4-input NAND gate |
| dlyc_1 | 7t-5V | 707 | Delay buffer |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (19k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
How this design grew
raybox-zero has been made on 7 shuttles since Sep 2023. Every version, oldest first, with this one in bold:
- Sep 2023 · Tiny Tapeout 4 raybox-zero — 4 × 2 tiles
- Jun 2024 · Tiny Tapeout 7 raybox-zero TT07 edition — 6 × 2 tiles
- Nov 2024 · Tiny Tapeout IHP 0.2 raybox-zero TTIHP0p2 edition — 4 × 2 tiles
- Nov 2025 · Tiny Tapeout GF 0.1 raybox-zero TT07 edition — in a shared block
- Nov 2025 · Tiny Tapeout GF 0.2 raybox-zero TTGF0p2 edition — 3 × 4 tiles
- Mar 2026 · Tiny Tapeout IHP 0.4 raybox-zero TTIHP0p4 edition — 6 × 2 tiles
- Jul 2026 · wafer.space Run 2 AMM1 raybox-zero wafer.space run 2 half height — 1 × ½ slot
Tiny Tapeout tile Google shuttle wafer.space die
From Tiny Tapeout tiles to a die of its own
raybox-zero began as tiles on Tiny Tapeout 4, and now has a die of its own on wafer.space Run 2.
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. AMM1 was accepted on this check.
All 17 steps passed, with 0 KLayout DRC errors, on 2026-07-15.
Every step
| Step | Accepted on, and latest check 554, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|
| KLayout.ReadLayout | passed |
| KLayout.CheckTopLevel | passed |
| KLayout.CheckSize | passed |
| KLayout.CheckPadMask | passed |
| KLayout.GenerateID | passed |
| KLayout.Render | passed |
| KLayout.Density | passed |
| Checker.KLayoutDensity | passed |
| KLayout.ZeroAreaPolygons | passed |
| Checker.KLayoutZeroAreaPolygons | passed |
| KLayout.Antenna | passed |
| Checker.KLayoutAntenna | passed |
| Magic.DRC | passed |
| Checker.MagicDRC | passed |
| KLayout.DRC | passed |
| Checker.KLayoutDRC | passed |
| KLayout.WriteLayout | passed |
| KLayout DRC errors | 0 |
| Magic DRC errors (advisory) | 0 |
| Files | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.