Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

raybox-zero TTGF0p2 edition

135 · Retro computing · 3 × 4 tiles

by algofoogle (Anton Maurovic)

Layout render of raybox-zero TTGF0p2 edition

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		21k (27% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		35k (46% of buffer maximum)
Core covered by logic59%
Transistor density
transistors per mm²		293k average, 298k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

TTGF0p2 v1.8-dev submission of 'simple VGA ray caster game demo' from TT07/TTCAD25a

Source repository Its page on Tiny TapeoutBuy this chip

Size1076 × 737 µm (0.793 mm²)
Macrott_um_algofoogle_raybox_zero
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles3 × 4 at column 0, row 6 of the tile grid
Mux address135
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors234,151
Logic cells16,500 + 29,025 filler and tap cells
Libraries 7t-5V (16k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

59%
39%
  • Logic cells 0.47 mm² (59%)
  • Filler and tap cells 0.31 mm² (39%)
  • Other 0.02 mm² (2%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,8702-input NAND gate
nor2_17t-5V 1,6252-input NOR gate
oai21_17t-5V 1,587OR-AND-Invert compound gate
aoi21_17t-5V 1,144AND-OR-Invert compound gate
xor2_17t-5V 9072-input XOR gate
dffq_47t-5V 812D flip-flop (1 bit storage, 4x drive)
buf_47t-5V 804Buffer (4x drive)
dffq_17t-5V 605D flip-flop (1 bit storage)
mux2_27t-5V 4592-input multiplexer (2x drive)
inv_17t-5V 436Inverter

Logic density map

211 logic cells, 2,754 transistors 281 logic cells, 2,907 transistors 247 logic cells, 2,839 transistors 218 logic cells, 2,851 transistors 179 logic cells, 2,918 transistors 270 logic cells, 2,976 transistors 251 logic cells, 2,910 transistors 248 logic cells, 2,861 transistors 294 logic cells, 2,873 transistors 252 logic cells, 2,720 transistors 92 logic cells, 1,728 transistors 217 logic cells, 2,792 transistors 274 logic cells, 3,081 transistors 243 logic cells, 3,130 transistors 191 logic cells, 3,125 transistors 227 logic cells, 3,181 transistors 243 logic cells, 3,101 transistors 265 logic cells, 3,121 transistors 243 logic cells, 3,037 transistors 317 logic cells, 3,056 transistors 338 logic cells, 3,047 transistors 205 logic cells, 2,093 transistors 176 logic cells, 2,805 transistors 252 logic cells, 3,100 transistors 242 logic cells, 2,991 transistors 213 logic cells, 3,092 transistors 183 logic cells, 3,285 transistors 245 logic cells, 3,182 transistors 234 logic cells, 3,069 transistors 200 logic cells, 3,110 transistors 271 logic cells, 3,110 transistors 271 logic cells, 2,897 transistors 117 logic cells, 1,882 transistors 175 logic cells, 2,804 transistors 225 logic cells, 2,979 transistors 217 logic cells, 2,988 transistors 229 logic cells, 3,091 transistors 219 logic cells, 3,088 transistors 215 logic cells, 3,210 transistors 263 logic cells, 3,194 transistors 188 logic cells, 2,998 transistors 186 logic cells, 2,766 transistors 177 logic cells, 2,750 transistors 80 logic cells, 1,985 transistors 214 logic cells, 2,852 transistors 217 logic cells, 3,014 transistors 214 logic cells, 3,132 transistors 230 logic cells, 3,222 transistors 224 logic cells, 3,011 transistors 255 logic cells, 3,031 transistors 236 logic cells, 3,018 transistors 225 logic cells, 2,794 transistors 187 logic cells, 2,704 transistors 195 logic cells, 2,811 transistors 92 logic cells, 1,999 transistors 168 logic cells, 2,720 transistors 213 logic cells, 3,062 transistors 216 logic cells, 2,984 transistors 214 logic cells, 3,006 transistors 199 logic cells, 2,893 transistors 199 logic cells, 3,002 transistors 228 logic cells, 3,040 transistors 168 logic cells, 3,177 transistors 155 logic cells, 3,230 transistors 142 logic cells, 3,130 transistors 80 logic cells, 2,084 transistors 189 logic cells, 2,946 transistors 203 logic cells, 3,023 transistors 197 logic cells, 3,056 transistors 193 logic cells, 3,014 transistors 225 logic cells, 3,164 transistors 209 logic cells, 3,079 transistors 150 logic cells, 3,184 transistors 144 logic cells, 3,178 transistors 144 logic cells, 3,195 transistors 113 logic cells, 3,007 transistors 74 logic cells, 2,026 transistors 28 logic cells, 796 transistors 60 logic cells, 915 transistors 86 logic cells, 1,035 transistors 76 logic cells, 1,008 transistors 73 logic cells, 963 transistors 53 logic cells, 953 transistors 52 logic cells, 1,041 transistors 50 logic cells, 1,042 transistors 26 logic cells, 886 transistors 0 logic cells, 737 transistors 0 logic cells, 510 transistors Densest SRAM-free 0.1 mm square: 351 logic cells 21k 28k 25k 22k 18k 27k 25k 25k 29k 25k 9k 22k 27k 24k 19k 23k 24k 26k 24k 32k 34k 20k 18k 25k 24k 21k 18k 24k 23k 20k 27k 27k 12k 17k 22k 22k 23k 22k 21k 26k 19k 19k 18k 8k 21k 22k 21k 23k 22k 25k 24k 22k 19k 19k 9k 17k 21k 22k 21k 20k 20k 23k 17k 15k 14k 8k 19k 20k 20k 19k 22k 21k 15k 14k 14k 11k 7k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (35k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

raybox-zero has been made on 7 shuttles since Sep 2023. Every version, oldest first, with this one in bold:

  1. Sep 2023 · Tiny Tapeout 4 raybox-zero — 4 × 2 tiles
  2. Jun 2024 · Tiny Tapeout 7 raybox-zero TT07 edition — 6 × 2 tiles
  3. Nov 2024 · Tiny Tapeout IHP 0.2 raybox-zero TTIHP0p2 edition — 4 × 2 tiles
  4. Nov 2025 · Tiny Tapeout GF 0.1 raybox-zero TT07 edition — in a shared block
  5. Nov 2025 · Tiny Tapeout GF 0.2 raybox-zero TTGF0p2 edition — 3 × 4 tiles
  6. Mar 2026 · Tiny Tapeout IHP 0.4 raybox-zero TTIHP0p4 edition — 6 × 2 tiles
  7. Jul 2026 · wafer.space Run 2 AMM1 raybox-zero wafer.space run 2 half height — 1 × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

raybox-zero started as a few tiles on Tiny Tapeout 4 and went on to a die of its own on wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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