Tiny Tapeout GF 0.2Die TTPG on wafer.space Run 1: the power-gated edition

52 projects on one chip, measured one by one and as a whole die

Buy this chip Put your design on the next one All its projects on tinytapeout.com

What was built

The chip as a whole: what its projects add up to.

This is the power-gated edition of Tiny Tapeout GF 0.2: it can switch off the power to the projects that are not selected. The same 52 projects were also made on the standard edition, without the power switches.

52

Projects

on the chip

52

Open source

with a public repository

2.8M

Transistors

across the unique designs

197k

Logic cells

gates and flip-flops

Counted inside the projects only, so these totals are smaller than the die's own figures on its run's page: the pads, Tiny Tapeout's multiplexer and controller, the power switches and the fill are left out.

Get this chip, or make your own

Tiny Tapeout puts many small designs on one chip. Start with a tile, then come back with a whole die.

Get this chip

It comes on a board you can plug in, with every project on it ready to try.

Buy this chip

Put your design on the next one

Tiny Tapeout GF 26c and 26d take projects until 7 December 2026, to be made on wafer.space Run 3.

Submit a project

Make a whole chip of your own

When a design outgrows a few tiles, it can have a die to itself on wafer.space Run 3: orders close 9 December 2026.

Reserve a slot

The die

519 391 135 134 038 039 295 551 517 549 515 130 547 513 385 384 129 128 001 000 032 033 288 545 577 481 609 579 451 194 483 610 611 581 197 196 101 485 612 613 583 455 454 199 198 102 103 358 359 487 614 615

Every design rendered from the layout at the same scale and placed where it sits on the 3.9 × 5.1 mm die. Point at a project to see its name, and select it for its details.Every project is listed further down.

Project sizes

How many tiles each project took. A tile is the smallest piece of a Tiny Tapeout chip you can submit a design to.

Total	52
1 × 1 tiles	26
1 × 2 tiles	13
2 × 2 tiles	4
3 × 2 tiles	2
3 × 4 tiles	4
4 × 2 tiles	2
4 × 4 tiles	1

Layout on GitHub

Shuttle status

Two schedules meet here: Tiny Tapeout collects the projects and builds the die, then wafer.space manufactures it on wafer.space Run 1 and ships the parts.

Done so far

Tiny Tapeout 24 November 2025 Tiny Tapeout GF 0.2 submissions close Last day to submit a project to this Tiny Tapeout shuttle
wafer.space 28 November 2025, 23:59 AoE Purchase deadline Final deadline to purchase manufacturing slots, for whole-die slots on the run (not Tiny Tapeout projects)
wafer.space 3 December 2025, 23:59 AoE Design submission Final deadline to submit GDS files for fabrication
Tiny Tapeout 11 December 2025 Tiny Tapeout GF 0.2 tapeout release Tiny Tapeout publishes the die's layout (tapeout-ws2512-powergate) and sends it to wafer.space
wafer.space 8 January 2026 Tape-out to GlobalFoundries GDS files delivered to GlobalFoundries for fabrication
wafer.space 6 April 2026 Wafers returned Wafers back from GlobalFoundries
wafer.space 10 April 2026 First wafers diced The first wafers cut into individual dies
wafer.space 17 April 2026 Remaining wafers diced The rest of the wafers diced
wafer.space 20 April 2026 First dies sorted Dies picked from the first wafers for the first shipments
wafer.space 21 April 2026 First bare dies shipped Initial bare dies shipped to customers
wafer.space 25 April 2026 First packaged parts shipped Initial chip-on-board packaged parts shipped
wafer.space 4 May 2026 Bare dies shipped Sorted dies from the main batch of wafers shipped

Still to come

Today, 24 October 2026
wafer.space 31 October 2026 (expected) Packaged parts shipped Chip-on-board packaged parts from the main batch of wafers shipped
wafer.space 5 November 2026 (expected) Last bare dies shipped Sorted dies from the last wafers shipped
wafer.space 5 December 2026 (expected) Last packaged parts shipped Chip-on-board packaged parts from the last wafers shipped

Missed this one? Tiny Tapeout GF 26c and 26d take projects until 7 December 2026: submit a project.

From the wafer.space run schedule and the Tiny Tapeout GF 0.2 repository.

How people used their silicon

Where the area of 52 projects (10 mm² of silicon) actually went

58%

38%

Logic cells 58% — gates and flip-flops doing the design's actual work
Filler and tap cells 38% — inserted by the tools to keep rows continuous and wells tied
Other 4% — routing channels, analog and custom layout, power grid and empty space

What people built

The kinds of design on this chip.

Other digital 25 Retro computing 7 Games 6 RISC-V and CPUs 6 Communications 3 Art and logos 2 First designs 1 Security 1 Test structures 1

Standard cell libraries

The ready-made gate libraries the designs were built from: how many tracks tall each cell is, and the voltage it runs at.

Standard cell library	Logic cells	Share
7t-5V gf180mcu_fd_sc_mcu7t5v0	194k	98%
9t-5V gf180mcu_fd_sc_mcu9t5v0	4k	2%

Area budget of every design

Each bar is one project, split the same way as above. Sorted by how much of the project is logic.

130 USB CDC (Serial) Device 359 Simple RISC-V 039 TinyQV RISC-V SoC 101 SCµM-BLE-RX 611 Video mode tester 288 Notre Dame - Lockpick Game TT Example 519 Simon Says memory game 032 Zedulo TestChip1 513 Classic 8-bit era Programmable Sound Generator SN76489 547 WokwiPWM 579 PRISM 8 with TinySnake 129 2x2 MAC Systolic array with DFT

Show all 52 projects

199 VGA Nyan Cat 391 megabytebeat 197 LISA 8-Bit Microcontroller 103 Simon's Caterpillar 545 Flame demo 455 Zilog Z80 198 easy PAL 135 raybox-zero TTGF0p2 edition 295 KianV uLinux SoC 102 Silly-Faust 551 PVTMonitorSuite 194 2048 sliding tile puzzle game (VGA) 033 wafer.space Logo VGA Screensaver 451 Asicle v2 481 ROTFPGA v2 196 Quickscope 515 VGA Tiny Logo 581 Register bank accessible through SPI and I2C 038 Wildcat RISC-V 549 Dog Battle Game 612 One Bit PUF 583 Cell mux 134 VGA Drop (audio/visual demo) 128 VGA clock 485 MarcoPolo 358 Notre Dame - CSE 30342 - DIC - Advanced FSM Final Project Example 609 Super-Simple-SPI-CPU 487 Linear Timecode (LTC) generator 483 7-Segment Digital Desk Clock 454 CAN Controller for Rocket 384 LEDs Racer 385 Frequency Counter SSD1306 OLED 614 Ring osc on VGA 000 Chip ROM 615 GF180MCU loopback tile with input skew measurement 001 Tiny Tapeout Factory Test 610 Example of Bad Synchronizer 517 Ring Oscillator (5 inverter) 613 DDR throughput and flop aperture test 577 PILIPINAS_IC

What fits on 1 mm² of GF180MCU silicon?

Theoretical maximum against what designers achieved

The maximum packs one cell type edge to edge with no room for wiring. Real designs need the wiring. Each box gives the most of a cell that fits with any GF180MCU library, then with the libraries this chip used.

~114k

Inverters per mm²

GF180MCU maximum,
with AS 7t-3.3V inv_2

With this chip's libraries:

7t-5V: 114k inv_1

9t-5V: 89k inv_1

~91k

NAND gates per mm²

GF180MCU maximum,
with 7t-5V nand2_1

With this chip's libraries:

7t-5V: 91k nand2_1

9t-5V: 71k nand2_1

~76k

Buffers per mm²

GF180MCU maximum,
with AS 7t-3.3V buff_2

With this chip's libraries:

7t-5V: 76k buf_1

9t-5V: 59k buf_1

~17k

Flip-flops per mm²

GF180MCU maximum,
with AS 7t-3.3V dfxtp_2

With this chip's libraries:

7t-5V: 16k dffq_1

9t-5V: 13k dffq_1

28k

Best core average

logic cells/mm² of core — 37% of the buffer maximum

SCµM-BLE-RX

42k

Densest 0.1 mm square

logic cells per mm² — 55% of the buffer maximum

megabytebeat

21k

Typical project

median logic cells/mm² of core across 36 digital projects (1,000 or more logic cells)

61% of the core covered by logic cells

Percentages compare with the buffer maximum for each design's own library: buffers are among the smallest and most common logic cells, so a design made only of buffers, packed edge to edge with no wiring, would reach 100%.

Sizing your own design

What each tile size held on this chip, and what it would hold at its densities

				Logic cells in its digital projects1,000 or more logic cells		Logic cells at this chip's density		Theoretical maximum, 7t-5V cells
Tiles	Size	Core area	Projects	Most	Median	Typical21k / mm²	Best28k / mm²	NAND gatesnand2_1	Flip-flopsdffq_1
1 × 1	0.35 × 0.16 mm	0.06 mm²	26	1.5k	1.2k	1.2k	1.6k	5.1k	880
1 × 2	0.35 × 0.33 mm	0.12 mm²	13	2.9k	2.2k	2.4k	3.3k	10.5k	1.8k
2 × 2	0.71 × 0.33 mm	0.23 mm²	4	4.9k	4.3k	4.9k	6.7k	21.3k	3.7k
3 × 2	1.08 × 0.33 mm	0.36 mm²	2	8.8k	7.3k	7.4k	10.1k	32.5k	5.6k
3 × 4	1.08 × 0.74 mm	0.80 mm²	4	22.7k	18.7k	16.6k	22.7k	72.8k	12.6k
4 × 2	1.44 × 0.33 mm	0.48 mm²	2	11.0k	10.4k	9.9k	13.5k	43.3k	7.5k
4 × 4	1.44 × 0.74 mm	1.07 mm²	1	20.3k	20.3k	22.2k	30.3k	97.1k	16.7k

Swipe the table sideways for more columns.

Core area is the whole project. "Typical" and "best" multiply the core area by this chip's median and best core densities; SRAM and analog blocks take their area out of that. The theoretical maxima fill the core with nothing but that one cell of 7t-5V, the library most used on this chip, edge to edge with no routing.

Pick the tile size your design needs when you submit it to the next Tiny Tapeout chip, by 7 December 2026.

Logic density of every digital design

A digital project here is one with 1,000 or more logic cells. Solid bar: average over the core. Outlined bar: the densest 0.1 mm square outside SRAM, per mm² (a dash where memory covers most of the design). The scale ends at the buffer theoretical maximum (76k cells/mm²). The numbers are core / densest, in logic cells per mm².

101 SCµM-BLE-RX 28k / 39k 519 Simon Says memory game 27k / 38k 547 WokwiPWM 26k / 33k 130 USB CDC (Serial) Device 25k / 34k 039 TinyQV RISC-V SoC 25k / 37k 579 PRISM 8 with TinySnake 25k / 33k 391 megabytebeat 25k / 42k 513 Classic 8-bit era Programmable Sound Generator SN76489 25k / 36k 288 Notre Dame - Lockpick Game TT Example 24k / 29k 129 2x2 MAC Systolic array with DFT 23k / 36k 359 Simple RISC-V 23k / 33k 199 VGA Nyan Cat 23k / 35k

Show all 36 digital projects

032 Zedulo TestChip1 22k / 31k 611 Video mode tester 22k / 27k 545 Flame demo 22k / 31k 197 LISA 8-Bit Microcontroller 22k / 32k 103 Simon's Caterpillar 22k / 32k 455 Zilog Z80 21k / 34k 102 Silly-Faust 21k / 36k 135 raybox-zero TTGF0p2 edition 21k / 35k 551 PVTMonitorSuite 20k / 32k 194 2048 sliding tile puzzle game (VGA) 20k / 38k 481 ROTFPGA v2 20k / 31k 515 VGA Tiny Logo 20k / 35k 033 wafer.space Logo VGA Screensaver 19k / 27k 295 KianV uLinux SoC 19k / 28k 549 Dog Battle Game 19k / 27k 358 Notre Dame - CSE 30342 - DIC - Advanced FSM Final Project Example 18k / 35k 451 Asicle v2 17k / 34k 038 Wildcat RISC-V 16k / 34k 198 easy PAL 16k / 26k 134 VGA Drop (audio/visual demo) 15k / 27k 196 Quickscope 15k / 29k 384 LEDs Racer 11k / 31k 454 CAN Controller for Rocket 11k / 26k 385 Frequency Counter SSD1306 OLED 10k / 30k

Every digital project's densities as a table

Project	Tiles	Library	Logic cells	Inside core per mm²	Densest 0.1 mm square per mm²	Core covered	Core mm²
SCµM-BLE-RX 101	3 × 4	7t-5V	22,709	28,415	39,300	74%	0.80*
Simon Says memory game 519	1 × 1	7t-5V	1,507	26,911	38,200	70%	0.06*
WokwiPWM 547	1 × 1	7t-5V	1,481	26,446	32,600	69%	0.06*
USB CDC (Serial) Device 130	1 × 2	7t-5V	2,943	25,481	34,000	78%	0.12*
TinyQV RISC-V SoC 039	3 × 4	7t-5V	20,084	25,130	36,900	74%	0.80*
PRISM 8 with TinySnake 579	1 × 1	7t-5V	1,401	25,018	32,900	69%	0.06*
megabytebeat 391	3 × 2	7t-5V	8,785	24,649	42,000	62%	0.36*
Classic 8-bit era Programmable Sound Generator SN76489 513	1 × 1	7t-5V	1,380	24,643	35,600	69%	0.06*
Notre Dame - Lockpick Game TT Example 288	1 × 2	7t-5V	2,722	23,567	28,800	71%	0.12*
2x2 MAC Systolic array with DFT 129	1 × 2	7t-5V	2,711	23,472	35,500	64%	0.12*
Simple RISC-V 359	4 × 2	7t-5V	11,000	23,148	32,800	78%	0.48*
VGA Nyan Cat 199	1 × 2	7t-5V	2,662	23,048	34,700	63%	0.12*
Zedulo TestChip1 032	1 × 1	7t-5V	1,242	22,179	31,000	69%	0.06*
Video mode tester 611	1 × 1	7t-5V	1,234	22,036	27,100	73%	0.06*
Flame demo 545	1 × 1	7t-5V	1,230	21,964	30,900	61%	0.06*
LISA 8-Bit Microcontroller 197	3 × 4	7t-5V	17,231	21,560	32,300	62%	0.80*
Simon's Caterpillar 103	1 × 2	7t-5V	2,486	21,524	31,600	62%	0.12*
Zilog Z80 455	2 × 2	7t-5V	4,918	20,990	33,500	61%	0.23*
Silly-Faust 102	4 × 2	7t-5V	9,814	20,652	35,800	56%	0.48*
raybox-zero TTGF0p2 edition 135	3 × 4	7t-5V	16,500	20,646	35,100	59%	0.80*
PVTMonitorSuite 551	1 × 1	7t-5V	1,123	20,054	31,500	55%	0.06*
2048 sliding tile puzzle game (VGA) 194	2 × 2	7t-5V	4,680	19,974	38,100	54%	0.23*
ROTFPGA v2 481	1 × 2	7t-5V	2,269	19,645	30,900	53%	0.12*
VGA Tiny Logo 515	1 × 1	7t-5V	1,095	19,554	34,700	51%	0.06*
wafer.space Logo VGA Screensaver 033	1 × 2	7t-5V	2,228	19,290	27,300	53%	0.12*
KianV uLinux SoC 295	4 × 4	7t-5V	20,266	19,018	28,000	58%	1.07*
Dog Battle Game 549	1 × 1	7t-5V	1,047	18,696	27,200	48%	0.06*
Notre Dame - CSE 30342 - DIC - Advanced FSM Final Project Example 358	1 × 2	7t-5V	2,044	17,697	35,400	43%	0.12*
Asicle v2 451	2 × 2	7t-5V	4,018	17,149	33,900	53%	0.23*
Wildcat RISC-V 038	3 × 2	7t-5V	5,867	16,462	33,900	48%	0.36*
easy PAL 198	1 × 2	7t-5V	1,890	16,364	26,200	61%	0.12*
VGA Drop (audio/visual demo) 134	2 × 2	9t-5V	3,625	15,472	27,200	45%	0.23*
Quickscope 196	1 × 2	7t-5V	1,718	14,874	29,400	52%	0.12*
LEDs Racer 384	1 × 2	7t-5V	1,315	11,385	31,300	32%	0.12*
CAN Controller for Rocket 454	1 × 2	7t-5V	1,218	10,545	26,400	36%	0.12*
Frequency Counter SSD1306 OLED 385	1 × 2	7t-5V	1,157	10,017	30,000	27%	0.12*

The projects

Every project on this chip: an index, then grouped by what it does. Select one for its layout, its measurements and any die photographs.

Project index

All 52 projects by their address on the chip's multiplexer, with how many tiles each took and how much logic it packs.

Address	Project	Author	Tiles	What it is	Logic cells	Cells per mm²
000	Chip ROM	Uri Shaked	1 × 1	Other digital	236	4k
001	Tiny Tapeout Factory Test	Tiny Tapeout	1 × 1	Test structures	90	2k
032	Zedulo TestChip1	Zedulo	1 × 1	Other digital	1,242	22k
033	wafer.space Logo VGA Screensaver	Uri Shaked	1 × 2	Art and logos	2,228	19k
038	Wildcat RISC-V	Martin Schoeberl · repository @schoeberl	3 × 2	RISC-V and CPUs	5,867	16k
039	TinyQV RISC-V SoC	Michael Bell · repository @MichaelBell	3 × 4	RISC-V and CPUs	20,084	25k
101	SCµM-BLE-RX	Dingyu Zhou · repository @ZDYnb	3 × 4	Communications	22,709	28k
102	Silly-Faust	Louis Ledoux, Cochard Pierre · repository @Bynaryman	4 × 2	Other digital	9,814	21k
103	Simon's Caterpillar	htfab · repository @htfab	1 × 2	Other digital	2,486	22k
128	VGA clock	Matt Venn · repository @mattvenn	1 × 1	Retro computing	860	15k
129	2x2 MAC Systolic array with DFT	Julia Desmazes · repository @Essenceia	1 × 2	Other digital	2,711	23k
130	USB CDC (Serial) Device	Uri Shaked · repository @urish	1 × 2	Communications	2,943	25k
134	VGA Drop (audio/visual demo)	ReJ aka Renaldas Zioma, eriQue aka Erik Hemming, Matthias Kampa · repository @rejunity	2 × 2	Retro computing	3,625	15k
135	raybox-zero TTGF0p2 edition	algofoogle (Anton Maurovic) · repository @algofoogle	3 × 4	Retro computing	16,500	21k
194	2048 sliding tile puzzle game (VGA)	Uri Shaked · repository @urish	2 × 2	Games	4,680	20k
196	Quickscope	Frans Skarman · repository @TheZoq2	1 × 2	Other digital	1,718	15k
197	LISA 8-Bit Microcontroller	Ken Pettit · repository @kdp1965	3 × 4	RISC-V and CPUs	17,231	22k
198	easy PAL	Ken Pettit · repository @kdp1965	1 × 2	Other digital	1,890	16k
199	VGA Nyan Cat	Andy Sloane · repository @a1k0n	1 × 2	Retro computing	2,662	23k
288	Notre Dame - Lockpick Game TT Example	Matthew Morrison · repository @mmorri22	1 × 2	Games	2,722	24k
295	KianV uLinux SoC	Hirosh Dabui	4 × 4	RISC-V and CPUs	20,266	19k
358	Notre Dame - CSE 30342 - DIC - Advanced FSM Final Project Example	Matthew Morrison · repository @mmorri22	1 × 2	Other digital	2,044	18k
359	Simple RISC-V	kinako71-2 · repository @urish	4 × 2	RISC-V and CPUs	11,000	23k
384	LEDs Racer	KerCrafter · repository @KerCrafter	1 × 2	Games	1,315	11k
385	Frequency Counter SSD1306 OLED	Pawel Sitarz (embelon) · repository @embelon	1 × 2	Other digital	1,157	10k
391	megabytebeat	proppy · repository @proppy	3 × 2	Other digital	8,785	25k
451	Asicle v2	htfab · repository @htfab	2 × 2	Other digital	4,018	17k
454	CAN Controller for Rocket	Noritsuna Imamura · repository @noritsuna	1 × 2	Communications	1,218	11k
455	Zilog Z80	ReJ aka Renaldas Zioma · repository @rejunity	2 × 2	Retro computing	4,918	21k
481	ROTFPGA v2	htfab · repository @htfab	1 × 2	Other digital	2,269	20k
483	7-Segment Digital Desk Clock	Samuel Ellicott · repository @sellicott	1 × 1	Other digital	746	13k
485	MarcoPolo	Javier Munoz Saez · repository @javiBajoCero	1 × 1	First designs	726	13k
487	Linear Timecode (LTC) generator	Thomas Flummer · repository @flummer	1 × 1	Other digital	777	14k
513	Classic 8-bit era Programmable Sound Generator SN76489	ReJ aka Renaldas Zioma · repository @rejunity	1 × 1	Other digital	1,380	25k
515	VGA Tiny Logo	Renaldas Zioma · repository @rejunity	1 × 1	Art and logos	1,095	20k
517	Ring Oscillator (5 inverter)	Darryl Miles · repository @dlmiles	1 × 1	Other digital	61	1k
519	Simon Says memory game	Uri Shaked · repository @urish	1 × 1	Games	1,507	27k
545	Flame demo	Konrad Beckmann & Linus Mårtensson · repository @kbeckmann	1 × 1	Other digital	1,230	22k
547	WokwiPWM	Ken Pettit · repository @kdp1965	1 × 1	Other digital	1,481	26k
549	Dog Battle Game	Sophus Andreassen · repository @jorgenkraghjakobsen	1 × 1	Games	1,047	19k
551	PVTMonitorSuite	Susumu Yamazaki · repository @zacky1972	1 × 1	Other digital	1,123	20k
577	PILIPINAS_IC	Alexander Co Abad and Dino Dominic Ligutan · repository @alexandercoabad	1 × 1	Other digital	82	1k
579	PRISM 8 with TinySnake	Ken Pettit · repository @kdp1965	1 × 1	Games	1,401	25k
581	Register bank accessible through SPI and I2C	Caio Alonso da Costa · repository @calonso88	1 × 1	Other digital	897	16k
583	Cell mux	htfab · repository @htfab	1 × 1	Other digital	677	12k
609	Super-Simple-SPI-CPU	James Ashie Kotey	1 × 1	RISC-V and CPUs	761	14k
610	Example of Bad Synchronizer	Darryl Miles project from Eric Smith · repository @dlmiles	1 × 1	Other digital	62	1k
611	Video mode tester	htfab · repository @htfab	1 × 1	Retro computing	1,234	22k
612	One Bit PUF	Yimin Gao and Ceylan Morgul · repository @Capulus123	1 × 1	Security	977	17k
613	DDR throughput and flop aperture test	Darryl Miles project from Eric Smith · repository @dlmiles	1 × 1	Other digital	90	2k
614	Ring osc on VGA	algofoogle (Anton Maurovic) · repository @algofoogle	1 × 1	Retro computing	473	8k
615	GF180MCU loopback tile with input skew measurement	Darryl Miles project from Eric Smith · repository @dlmiles	1 × 1	Other digital	81	1k

Show all 52 projectsShow the first 16 only

Swipe the table sideways for more columns.

Designs that grew

Some designs on this chip have been made many times, on earlier and later Tiny Tapeout chips, and several now have a whole die of their own on a wafer.space run. The ringed marker is this chip.

TinyQV RISC-V SoC 039

KianV RISC-V Linux SoC 295 KianV uLinux SoC

raybox-zero 135 raybox-zero TTGF0p2 edition

Open-source Z80 455 Zilog Z80

Tiny Tapeout tile Google shuttle wafer.space die this chip
Each marker is one version of the design: hover over it or focus it for details, and select it to open its page. On a phone, the table below lists every one.

As a table

Design	Made on	When	Version	Size
TinyQV RISC-V SoC	Tiny Tapeout 6	Apr 2024	TinyQV RISC-V SoC	2 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	TinyQV RISC-V SoC	2 × 2 tiles
	Tiny Tapeout IHP 25a	Mar 2025	TinyQV RISC-V SoC	3 × 2 tiles
	Tiny Tapeout IHP 25b	Sep 2025	TinyQV - Crowdsourced RISC-V SoC	5 × 4 tiles
	Tiny Tapeout SKY 25a	Sep 2025	TinyQV 'Asteroids' - Crowdsourced RISC-V SoC; TinyQV 'Berzerk' - Crowdsourced RISC-V SoC	8 × 4 tiles, 4 × 4 tiles
	Tiny Tapeout SKY 25b	Nov 2025	TinyQV RISC-V SoC	3 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	TinyQV RISC-V SoC	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	TinyQV RISC-V SoC	3 × 4 tiles
	wafer.space Run 1	Dec 2025	TQVA TinyQV - Crowdsourced RISC-V SoC; TQVB TinyQV - Crowdsourced RISC-V SoC (0.5x1); TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5)	TQVA ½ × ½ slot, TQVB ½ × 1 slot, TQVC 1 × ½ slot
	Tiny Tapeout GF 0.3	Jun 2026	TinyQV RISC-V SoC	4 × 2 tiles
	wafer.space Run 2	Jul 2026	TQVA TinyQV - Crowdsourced RISC-V SoC; TQVC TinyQV - Crowdsourced RISC-V SoC (1x0.5); TQVD TinyQV - RISC-V SoC with HDMI output; TQVE TinyQV - RISC-V SoC with experimental pad setup	TQVA ½ × ½ slot, TQVC 1 × ½ slot, TQVD ½ × ½ slot, TQVE ½ × ½ slot
KianV RISC-V Linux SoC	Tiny Tapeout 5	Nov 2023	KianV uLinux SoC	8 × 2 tiles
	Tiny Tapeout 6	Apr 2024	KianV uLinux SoC	8 × 2 tiles
	Tiny Tapeout 7	Jun 2024	KianV RISC-V RV32E Baremetal SoC	3 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	KianV RISC-V RV32E Baremetal SoC	4 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	KianV uLinux SoC	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	KianV uLinux SoC	4 × 4 tiles
	wafer.space Run 1	Dec 2025	KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU	1 × 1 slot
	Tiny Tapeout IHP 26a	Mar 2026	KianV SV32 TT Linux SoC	8 × 4 tiles
	Tiny Tapeout GF 0.3	Jun 2026	KianV uLinux SoC	4 × 4 tiles
	wafer.space Run 2	Jul 2026	KIAN KianV: A 32-bit RISC-V Linux SoC taped out on GF180MCU Run 2	1 × 1 slot
raybox-zero	Tiny Tapeout 4	Sep 2023	raybox-zero	4 × 2 tiles
	Tiny Tapeout 7	Jun 2024	raybox-zero TT07 edition	6 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	raybox-zero TTIHP0p2 edition	4 × 2 tiles
	Tiny Tapeout GF 0.1	Nov 2025	raybox-zero TT07 edition	in a shared block
	Tiny Tapeout GF 0.2	Nov 2025	raybox-zero TTGF0p2 edition	3 × 4 tiles
	Tiny Tapeout IHP 0.4	Mar 2026	raybox-zero TTIHP0p4 edition	6 × 2 tiles
	wafer.space Run 2	Jul 2026	AMM1 raybox-zero wafer.space run 2 half height	1 × ½ slot
Open-source Z80	Tiny Tapeout 7	Jun 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout IHP 0.2	Nov 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout 9	Nov 2024	Zilog Z80	2 × 2 tiles
	Tiny Tapeout IHP 25a	Mar 2025	Zilog Z80	2 × 2 tiles
	Tiny Tapeout GF 0.2	Nov 2025	Zilog Z80	2 × 2 tiles
	wafer.space Run 1	Dec 2025	HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot); RZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU	HZ80 ½ × 1 slot, RZ80 1 × 1 slot
	wafer.space Run 2	Jul 2026	HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot); QZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot)	HZ80 ½ × 1 slot, QZ80 ½ × ½ slot

1 × 1 tile · 90 logic cells

5 V

GF180MCU loopback tile with input skew measurement

1 × 1 tile · 81 logic cells

1 × 1 tile · 1k logic cells

5 V

Ring osc on VGA

1 × 1 tile · 473 logic cells

1 × 1 tile · 1k logic cells

1 × 1 tile · 761 logic cells

5 V

Communications 3

SCµM-BLE-RX

3 × 4 tiles · 23k logic cells

5 V

USB CDC (Serial) Device

1 × 2 tiles · 3k logic cells

5 V

CAN Controller for Rocket

1 × 2 tiles · 1k logic cells

5 V

Art and logos 2

033

wafer.space Logo VGA Screensaver

1 × 2 tiles · 2k logic cells

5 V

The die as a whole, measured like every other design on its run: its size, pads, process features, density, precheck and photographs. See every design on wafer.space Run 1

Layout render of Tiny Tapeout GF 0.2, power-gated

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core logic cells per mm²	16k (21% of buffer maximum) over the 12.90 mm² core: what the design itself packed
Inside the seal ring logic cells per mm²	10k over all 19.65 mm² of the slot, pad ring included
Densest mm² logic cells per mm²	26k (34% of buffer maximum)
Core covered by logic	46%
Transistor density transistors per mm²	252k average, 310k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

https://www.tinytapeout.com

Source repository

Die	3.93 × 5.12 mm (20.1 mm²)
Core area	12.90 mm² inside the pad ring the project template's, 442 µm in from each edge
Inside the seal ring	19.65 mm² (the die less its 26 µm seal ring)
Placements	1 on the reticle, in slot D4
Bond pads	74
Transistors	3,254,189
Logic cells	203,780 + 366,311 filler and tap cells
Libraries	7t-5V (200k), 9t-5V (4k)
SRAM	No SRAM

Submission

Licence	Apache-2.0 declared Repository: Apache-2.0 in LICENSE — agrees
How it was checked	Commit and PDK pin The licence and template were read from the repository at commit 4150e9654790.
Chip-on-board	Not selected at submission
Precheck	Passed the check it was accepted on, 2025-12-11 Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V	18,377 custom transistors
5 V	7t-5V standard cells, 9t-5V standard cells
Gate oxides	Thin (3.3 V) and thick (5 V/6 V) in the design itself
I/O library	gf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

30%

25%

10%

36%

Logic cells 5.96 mm² (30%)
Filler and tap cells 4.98 mm² (25%)
Other 1.96 mm² (10%)
Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

Cell	Library	Instances	What it does
nand2_1	7t-5V	23,817	2-input NAND gate
oai21_1	7t-5V	14,104	OR-AND-Invert compound gate
nor2_1	7t-5V	13,214	2-input NOR gate
aoi21_1	7t-5V	11,441	AND-OR-Invert compound gate
dffq_1	7t-5V	10,148	D flip-flop (1 bit storage)
xor2_1	7t-5V	7,614	2-input XOR gate
buf_2	7t-5V	7,068	Buffer (2x drive)
buf_4	7t-5V	6,477	Buffer (4x drive)
dffq_4	7t-5V	6,262	D flip-flop (1 bit storage, 4x drive)
mux2_2	7t-5V	5,990	2-input multiplexer (2x drive)

Logic density map

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (26k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. TTPG was accepted on this check, and has been checked again since with newer rules.

All 16 steps passed, with 0 KLayout DRC errors, on the latest re-run, 2026-08-02 (accepted on 2025-12-11).

Every step, and the latest re-run

Step	Accepted on check 68, 2025-12-11, initial	Latest re-run check 761, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayout	—	passed
KLayout.CheckTopLevel	—	passed
KLayout.CheckSize	—	passed
KLayout.GenerateID	—	passed
KLayout.Render	—	passed
KLayout.Density	—	passed
Checker.KLayoutDensity	—	passed
KLayout.ZeroAreaPolygons	—	passed
Checker.KLayoutZeroAreaPolygons	—	passed
KLayout.Antenna	—	passed
Checker.KLayoutAntenna	—	passed
Magic.DRC	—	passed
Checker.MagicDRC	—	passed
KLayout.DRC	—	passed
Checker.KLayoutDRC	—	passed
KLayout.WriteLayout	—	passed
KLayout DRC errors		0
Magic DRC errors (advisory)		0
Files	The platform no longer stores this check's results.	steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Data and method

Everything on this page is measured from the public layout; the dates come from the published schedules.

Logic cells are standard cell instances, excluding fillers, taps, antenna diodes and tie cells.
Transistors are places where gate polysilicon crosses diffusion, not counting dummy fill.
Core area is the whole project.
Bond pads are the pad openings in the pad ring, or in a second ring of pads inside it for chip-on-board bonding; probe pads are the others, next to the blocks they test. Letters and logos on the pad layer are not pads.
Theoretical maximum tiles one cell at its placement boundary with no routing.
Densest 0.1 mm square is the best 0.1 mm square anywhere in each die, sliding in 20 µm steps and avoiding SRAM, given per mm².

The full written analysis is the density report. The measurements behind it:

Generated by ws-run-reports from layout/TTPG.oas (md5 b6494ef5f5770752906c875739b2f09f).

What is Tiny Tapeout?

Tiny Tapeout is the quickest and cheapest way to get your own design made on a real chip.

Many designs share one Tiny Tapeout chip. Each project gets one or more small tiles, and a multiplexer on the chip connects the one you choose to the pins. Draw your first design in the browser with no experience by following the digital design guide, or write it in Verilog or another HDL; Tiny Tapeout's templates build and check it on GitHub. The chip comes on a demo board that selects your design and drives it.

Tiny Tapeout also runs workshops and supports teaching in universities and schools. Browse every Tiny Tapeout chip and the projects proven in silicon, or read the Tiny Tapeout FAQ.

Buy this chip All its projects on tinytapeout.com

The Tiny Tapeout demo board, with the socket in the middle where the chip's breakout card plugs in — Tiny Tapeout chips come on a breakout card that plugs into the middle of the demo board. Its RP2350 selects a project and drives its clock; the DIP switches, the seven-segment display and the Pmod headers connect to the project's pins. Render: Tiny Tapeout, tt-demo-pcb, Apache 2.0.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.