Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

wafer.space Logo VGA Screensaver

033 · Art and logos · 1 × 2 tiles

by Uri Shaked

Layout render of wafer.space Logo VGA Screensaver

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		19k (25% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		27k (36% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		280k average, 344k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Wafer.space Logo bouncing around the screen (640x480, TinyVGA Pmod)

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_waferspace_vga_screensaver
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 3, row 11 of the tile grid
Mux address33
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors32,311
Logic cells2,228 + 4,301 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

53%
42%
  • Logic cells 0.06 mm² (53%)
  • Filler and tap cells 0.05 mm² (42%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 2302-input NAND gate
oai21_17t-5V 154OR-AND-Invert compound gate
aoi21_17t-5V 144AND-OR-Invert compound gate
nor2_17t-5V 1052-input NOR gate
oai211_17t-5V 90OR-AND-Invert compound gate
nand3_17t-5V 783-input NAND gate
buf_27t-5V 73Buffer (2x drive)
clkbuf_47t-5V 67Clock buffer (4x drive)
xor2_17t-5V 562-input XOR gate
dffq_17t-5V 55D flip-flop (1 bit storage)

Logic density map

187 logic cells, 2,836 transistors 215 logic cells, 3,043 transistors 229 logic cells, 3,068 transistors 90 logic cells, 1,196 transistors 225 logic cells, 3,112 transistors 256 logic cells, 3,374 transistors 236 logic cells, 2,896 transistors 93 logic cells, 1,259 transistors 195 logic cells, 2,773 transistors 177 logic cells, 2,879 transistors 158 logic cells, 2,748 transistors 72 logic cells, 1,209 transistors 20 logic cells, 525 transistors 21 logic cells, 563 transistors 37 logic cells, 565 transistors 17 logic cells, 265 transistors Densest SRAM-free 0.1 mm square: 273 logic cells 19k 21k 23k 22k 26k 24k 19k 18k 16k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (27k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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