Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

MarcoPolo

485 · First designs · 1 × 1 tile

by Javier Munoz Saez · repository @javiBajoCero

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

726 logic cells: too few for density figures, which are given for projects of 1,000 or more.

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

when this UART receives 'MARCO' answers ' POLO! ' , adapted from https://github.com/javiBajoCero/ttihp-verilog-template

Source repository Its page on Tiny Tapeout Buy this chip

Size	347 × 161 µm (0.056 mm²)
Macro	tt_um_javibajocero_top
Files	documentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles	1 × 1 at column 6, row 17 of the tile grid
Mux address	485
Language	Verilog
Clock	50 MHz
Built with	LibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors	14,620
Logic cells	726 + 1,727 filler and tap cells
Libraries	7t-5V (726)
SRAM	No SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V	7t-5V standard cells
Gate oxides	Thick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

44%

48%

Logic cells 0.02 mm² (44%)
Filler and tap cells 0.03 mm² (48%)
Other 4,033 µm² (7%)

Most used cells

The ten standard cells this design uses most.

Cell	Library	Instances	What it does
dffrnq_1	7t-5V	153	D flip-flop with reset
nand2_1	7t-5V	76	2-input NAND gate
nor2_1	7t-5V	47	2-input NOR gate
aoi21_1	7t-5V	43	AND-OR-Invert compound gate
clkinv_1	7t-5V	41	Clock inverter
mux2_2	7t-5V	39	2-input multiplexer (2x drive)
xor2_1	7t-5V	25	2-input XOR gate
oai21_1	7t-5V	23	OR-AND-Invert compound gate
aoi22_1	7t-5V	22	AND-OR-Invert (2x2 inputs)
clkbuf_8	7t-5V	21	Clock buffer (8x drive)

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.