Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

easy PAL

198 · Other digital · 1 × 2 tiles

by Ken Pettit

Layout render of easy PAL

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		16k (22% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		26k (35% of buffer maximum)
Core covered by logic61%
Transistor density
transistors per mm²		291k average, 331k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

This is a simple PAL (by Matthias Musch) using shift-register based configuration

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_MATTHIAS_M_PAL_TOP_WRAPPER
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 7, row 7 of the tile grid
Mux address198
LanguageVerilog
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors33,566
Logic cells1,890 + 2,935 filler and tap cells
Libraries 7t-5V (2k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

61%
33%
  • Logic cells 0.07 mm² (61%)
  • Filler and tap cells 0.04 mm² (33%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
and2_17t-5V 6042-input AND gate
dffq_17t-5V 598D flip-flop (1 bit storage)
mux2_27t-5V 1432-input multiplexer (2x drive)
clkbuf_27t-5V 68Clock buffer (2x drive)
buf_27t-5V 65Buffer (2x drive)
aoi22_17t-5V 61AND-OR-Invert (2x2 inputs)
buf_17t-5V 31Buffer
aoi22_27t-5V 28AND-OR-Invert (2x2 inputs, 2x drive)
clkinv_17t-5V 26Clock inverter
or4_27t-5V 214-input OR gate (2x drive)

Logic density map

0 logic cells, 2,031 transistors 125 logic cells, 2,702 transistors 155 logic cells, 2,956 transistors 40 logic cells, 1,096 transistors 106 logic cells, 2,600 transistors 230 logic cells, 3,402 transistors 230 logic cells, 3,476 transistors 98 logic cells, 1,484 transistors 190 logic cells, 3,023 transistors 225 logic cells, 3,371 transistors 219 logic cells, 3,567 transistors 100 logic cells, 1,490 transistors 33 logic cells, 554 transistors 65 logic cells, 720 transistors 55 logic cells, 752 transistors 19 logic cells, 342 transistors Densest SRAM-free 0.1 mm square: 262 logic cells 0 12k 15k 11k 23k 23k 19k 22k 22k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (26k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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