Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

VGA Nyan Cat

199 · Retro computing · 1 × 2 tiles

by Andy Sloane

Layout render of VGA Nyan Cat

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		23k (30% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		35k (46% of buffer maximum)
Core covered by logic63%
Transistor density
transistors per mm²		289k average, 352k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Displays the classic nyan.cat animation

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_a1k0n_nyancat
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 7, row 6 of the tile grid
Mux address199
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors33,356
Logic cells2,662 + 3,786 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

63%
31%
  • Logic cells 0.07 mm² (63%)
  • Filler and tap cells 0.04 mm² (31%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3372-input NAND gate
nor2_17t-5V 2032-input NOR gate
oai21_17t-5V 152OR-AND-Invert compound gate
aoi21_17t-5V 135AND-OR-Invert compound gate
xor2_17t-5V 1172-input XOR gate
nand3_17t-5V 673-input NAND gate
clkinv_17t-5V 66Clock inverter
dffrnq_17t-5V 65D flip-flop with reset
clkbuf_47t-5V 60Clock buffer (4x drive)
and2_17t-5V 582-input AND gate

Logic density map

188 logic cells, 2,565 transistors 199 logic cells, 2,705 transistors 217 logic cells, 2,835 transistors 101 logic cells, 1,234 transistors 185 logic cells, 2,798 transistors 277 logic cells, 3,313 transistors 314 logic cells, 3,191 transistors 113 logic cells, 1,310 transistors 206 logic cells, 2,881 transistors 281 logic cells, 3,584 transistors 309 logic cells, 3,474 transistors 120 logic cells, 1,375 transistors 28 logic cells, 547 transistors 40 logic cells, 606 transistors 54 logic cells, 667 transistors 30 logic cells, 271 transistors Densest SRAM-free 0.1 mm square: 347 logic cells 19k 20k 22k 18k 28k 31k 21k 28k 31k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (35k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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