Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

USB CDC (Serial) Device

130 · Communications · 1 × 2 tiles

by Uri Shaked

Layout render of USB CDC (Serial) Device

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		25k (34% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic78%
Transistor density
transistors per mm²		310k average, 354k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

USB to UART bridge, 115200 baud rate

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_urish_usb_cdc
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 2, row 7 of the tile grid
Mux address130
LanguageVerilog
Clock48 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors35,855
Logic cells2,943 + 2,885 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

78%
16%
  • Logic cells 0.09 mm² (78%)
  • Filler and tap cells 0.02 mm² (16%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffrnq_17t-5V 339D flip-flop with reset
nand2_17t-5V 3212-input NAND gate
nor2_17t-5V 2232-input NOR gate
oai21_17t-5V 190OR-AND-Invert compound gate
clkinv_17t-5V 162Clock inverter
aoi21_17t-5V 129AND-OR-Invert compound gate
clkbuf_87t-5V 96Clock buffer (8x drive)
mux2_27t-5V 912-input multiplexer (2x drive)
aoi22_17t-5V 84AND-OR-Invert (2x2 inputs)
xor2_17t-5V 812-input XOR gate

Logic density map

203 logic cells, 3,040 transistors 272 logic cells, 3,173 transistors 262 logic cells, 3,087 transistors 110 logic cells, 1,306 transistors 231 logic cells, 3,115 transistors 332 logic cells, 3,469 transistors 296 logic cells, 3,506 transistors 120 logic cells, 1,399 transistors 266 logic cells, 3,139 transistors 277 logic cells, 3,444 transistors 263 logic cells, 3,422 transistors 106 logic cells, 1,444 transistors 57 logic cells, 664 transistors 57 logic cells, 664 transistors 55 logic cells, 692 transistors 36 logic cells, 291 transistors Densest SRAM-free 0.1 mm square: 340 logic cells 20k 27k 26k 23k 33k 30k 27k 28k 26k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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