Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

Zilog Z80

455 · Retro computing · 2 × 2 tiles

by ReJ aka Renaldas Zioma

Layout render of Zilog Z80

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		21k (28% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (44% of buffer maximum)
Core covered by logic61%
Transistor density
transistors per mm²		295k average, 284k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Z80 open-source silicon. Goal is to become a silicon proven, pin compatible, open-source replacement for classic Z80.

Source repository Its page on Tiny TapeoutBuy this chip

Size711 × 325 µm (0.231 mm²)
Macrott_um_rejunity_z80
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles2 × 2 at column 7, row 2 of the tile grid
Mux address455
LanguageVerilog
Clock4 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors69,170
Logic cells4,918 + 7,193 filler and tap cells
Libraries 7t-5V (5k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

61%
35%
  • Logic cells 0.14 mm² (61%)
  • Filler and tap cells 0.08 mm² (35%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 6392-input NAND gate
oai21_17t-5V 294OR-AND-Invert compound gate
aoi21_17t-5V 224AND-OR-Invert compound gate
nor2_17t-5V 2242-input NOR gate
mux2_27t-5V 1842-input multiplexer (2x drive)
buf_27t-5V 164Buffer (2x drive)
dffq_17t-5V 151D flip-flop (1 bit storage)
oai211_17t-5V 151OR-AND-Invert compound gate
aoi22_17t-5V 138AND-OR-Invert (2x2 inputs)
nand3_17t-5V 1333-input NAND gate

Logic density map

117 logic cells, 2,528 transistors 203 logic cells, 2,897 transistors 297 logic cells, 2,851 transistors 315 logic cells, 2,855 transistors 255 logic cells, 2,855 transistors 171 logic cells, 3,021 transistors 124 logic cells, 2,907 transistors 0 logic cells, 137 transistors 256 logic cells, 2,935 transistors 245 logic cells, 3,238 transistors 208 logic cells, 2,944 transistors 275 logic cells, 3,270 transistors 301 logic cells, 3,300 transistors 277 logic cells, 3,520 transistors 173 logic cells, 3,165 transistors 0 logic cells, 147 transistors 265 logic cells, 2,951 transistors 253 logic cells, 3,459 transistors 259 logic cells, 3,567 transistors 221 logic cells, 3,171 transistors 246 logic cells, 3,321 transistors 144 logic cells, 3,026 transistors 66 logic cells, 2,682 transistors 0 logic cells, 153 transistors 31 logic cells, 580 transistors 67 logic cells, 713 transistors 58 logic cells, 725 transistors 39 logic cells, 589 transistors 52 logic cells, 679 transistors 0 logic cells, 475 transistors 0 logic cells, 476 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 335 logic cells 12k 20k 30k 31k 25k 17k 12k 26k 24k 21k 27k 30k 28k 17k 26k 25k 26k 22k 25k 14k 7k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Open-source Z80 has been made on 7 shuttles since Jun 2024. Every version, oldest first, with this one in bold:

  1. Jun 2024 · Tiny Tapeout 7 Zilog Z80 — 2 × 2 tiles
  2. Nov 2024 · Tiny Tapeout IHP 0.2 Zilog Z80 — 2 × 2 tiles
  3. Nov 2024 · Tiny Tapeout 9 Zilog Z80 — 2 × 2 tiles
  4. Mar 2025 · Tiny Tapeout IHP 25a Zilog Z80 — 2 × 2 tiles
  5. Nov 2025 · Tiny Tapeout GF 0.2 Zilog Z80 — 2 × 2 tiles
  6. Dec 2025 · wafer.space Run 1 HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot) — ½ × 1 slot RZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU — 1 × 1 slot
  7. Jul 2026 · wafer.space Run 2 HZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 1 slot) — ½ × 1 slot QZ80 FOSSi open-source replacement for Z80 classic 8-bit CPU (0.5 x 0.5 slot) — ½ × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

Open-source Z80 started as a few tiles on Tiny Tapeout 7 and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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