Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

CAN Controller for Rocket

454 · Communications · 1 × 2 tiles

by Noritsuna Imamura

Layout render of CAN Controller for Rocket

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		11k (14% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		26k (35% of buffer maximum)
Core covered by logic36%
Transistor density
transistors per mm²		252k average, 313k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

CAN Controller for Rocket

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_noritsuna_CAN_CTRL
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 7, row 3 of the tile grid
Mux address454
LanguageVerilog
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors29,075
Logic cells1,218 + 3,515 filler and tap cells
Libraries 7t-5V (1k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

36%
57%
  • Logic cells 0.04 mm² (36%)
  • Filler and tap cells 0.07 mm² (57%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
clkinv_17t-5V 195Clock inverter
xor3_17t-5V 1893-input XOR gate
xor2_17t-5V 1172-input XOR gate
dffrnq_17t-5V 87D flip-flop with reset
mux2_27t-5V 652-input multiplexer (2x drive)
buf_27t-5V 55Buffer (2x drive)
dffrnq_27t-5V 54D flip-flop with reset (2x drive)
nor2_17t-5V 482-input NOR gate
nand2_17t-5V 422-input NAND gate
oai21_17t-5V 34OR-AND-Invert compound gate

Logic density map

0 logic cells, 2,031 transistors 51 logic cells, 2,374 transistors 47 logic cells, 2,320 transistors 2 logic cells, 895 transistors 18 logic cells, 2,156 transistors 148 logic cells, 3,054 transistors 155 logic cells, 3,083 transistors 70 logic cells, 1,189 transistors 84 logic cells, 2,460 transistors 186 logic cells, 3,064 transistors 197 logic cells, 3,102 transistors 95 logic cells, 1,288 transistors 13 logic cells, 496 transistors 59 logic cells, 627 transistors 68 logic cells, 664 transistors 25 logic cells, 272 transistors Densest SRAM-free 0.1 mm square: 264 logic cells 0 5k 5k 2k 15k 15k 8k 19k 20k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (26k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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