Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

Asicle v2

451 · Other digital · 2 × 2 tiles

by htfab

Layout render of Asicle v2

Rendered from the layout at 0.44 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		17k (23% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic53%
Transistor density
transistors per mm²		283k average, 331k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Wordle clone in raw silicon

Source repository Its page on Tiny TapeoutBuy this chip

Size711 × 325 µm (0.231 mm²)
Macrott_um_htfab_asicle2
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles2 × 2 at column 5, row 2 of the tile grid
Mux address451
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors66,358
Logic cells4,018 + 6,871 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

53%
43%
  • Logic cells 0.12 mm² (53%)
  • Filler and tap cells 0.10 mm² (43%)
  • Other 0.01 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 595D flip-flop (1 bit storage)
nand2_17t-5V 3022-input NAND gate
nor2_17t-5V 2462-input NOR gate
mux2_27t-5V 2452-input multiplexer (2x drive)
aoi21_17t-5V 217AND-OR-Invert compound gate
aoi22_17t-5V 193AND-OR-Invert (2x2 inputs)
clkinv_17t-5V 186Clock inverter
oai21_17t-5V 144OR-AND-Invert compound gate
xor2_17t-5V 1292-input XOR gate
nor3_17t-5V 1123-input NOR gate

Logic density map

68 logic cells, 2,377 transistors 154 logic cells, 2,813 transistors 179 logic cells, 3,171 transistors 178 logic cells, 3,013 transistors 122 logic cells, 3,034 transistors 2 logic cells, 2,128 transistors 0 logic cells, 2,129 transistors 0 logic cells, 147 transistors 229 logic cells, 3,059 transistors 288 logic cells, 3,157 transistors 261 logic cells, 3,609 transistors 298 logic cells, 3,258 transistors 219 logic cells, 3,227 transistors 130 logic cells, 2,647 transistors 0 logic cells, 2,213 transistors 0 logic cells, 153 transistors 234 logic cells, 3,073 transistors 276 logic cells, 3,153 transistors 271 logic cells, 3,278 transistors 221 logic cells, 3,068 transistors 202 logic cells, 3,258 transistors 212 logic cells, 3,052 transistors 117 logic cells, 2,591 transistors 0 logic cells, 153 transistors 46 logic cells, 631 transistors 46 logic cells, 679 transistors 48 logic cells, 684 transistors 51 logic cells, 670 transistors 62 logic cells, 653 transistors 65 logic cells, 660 transistors 39 logic cells, 587 transistors 0 logic cells, 33 transistors Densest SRAM-free 0.1 mm square: 339 logic cells 7k 15k 18k 18k 12k <1k 0 23k 29k 26k 30k 22k 13k 0 23k 28k 27k 22k 20k 21k 12k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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