Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

megabytebeat

391 · Other digital · 3 × 2 tiles

by proppy

Layout render of megabytebeat

Rendered from the layout at 0.67 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		25k (32% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		42k (55% of buffer maximum)
Core covered by logic62%
Transistor density
transistors per mm²		295k average, 348k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Best-of compilation of bytebeat 2011's greatest hits on-a-chip.

Source repository Its page on Tiny TapeoutBuy this chip

Size1076 × 325 µm (0.350 mm²)
Macrott_um_proppy_megabytebeat
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles3 × 2 at column 0, row 2 of the tile grid
Mux address391
Languagexls
Clock2.048 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors104,977
Logic cells8,785 + 8,464 filler and tap cells
Libraries 7t-5V (9k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

62%
33%
  • Logic cells 0.22 mm² (62%)
  • Filler and tap cells 0.12 mm² (33%)
  • Other 0.02 mm² (5%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,0412-input NAND gate
nor2_17t-5V 7732-input NOR gate
xor2_17t-5V 6202-input XOR gate
aoi21_17t-5V 491AND-OR-Invert compound gate
oai21_17t-5V 416OR-AND-Invert compound gate
clkinv_17t-5V 367Clock inverter
and2_17t-5V 3172-input AND gate
mux2_27t-5V 3032-input multiplexer (2x drive)
or2_17t-5V 2532-input OR gate
dffnq_17t-5V 211D flip-flop (falling edge)

Logic density map

12 logic cells, 2,072 transistors 19 logic cells, 2,163 transistors 329 logic cells, 3,160 transistors 337 logic cells, 3,445 transistors 370 logic cells, 3,355 transistors 347 logic cells, 3,315 transistors 371 logic cells, 3,343 transistors 352 logic cells, 3,394 transistors 340 logic cells, 3,383 transistors 337 logic cells, 3,164 transistors 105 logic cells, 1,728 transistors 301 logic cells, 2,872 transistors 321 logic cells, 3,159 transistors 324 logic cells, 3,230 transistors 349 logic cells, 3,468 transistors 367 logic cells, 3,522 transistors 350 logic cells, 3,588 transistors 391 logic cells, 3,342 transistors 301 logic cells, 3,677 transistors 307 logic cells, 3,757 transistors 409 logic cells, 3,462 transistors 135 logic cells, 2,015 transistors 184 logic cells, 2,682 transistors 299 logic cells, 3,099 transistors 262 logic cells, 3,217 transistors 336 logic cells, 3,308 transistors 318 logic cells, 3,313 transistors 153 logic cells, 2,812 transistors 16 logic cells, 2,264 transistors 109 logic cells, 2,568 transistors 177 logic cells, 2,890 transistors 245 logic cells, 3,076 transistors 5 logic cells, 1,528 transistors 0 logic cells, 446 transistors 35 logic cells, 544 transistors 63 logic cells, 683 transistors 62 logic cells, 646 transistors 43 logic cells, 572 transistors 3 logic cells, 481 transistors 0 logic cells, 476 transistors 0 logic cells, 477 transistors 0 logic cells, 474 transistors 1 logic cells, 477 transistors 0 logic cells, 330 transistors Densest SRAM-free 0.1 mm square: 420 logic cells 1k 2k 33k 34k 37k 35k 37k 35k 34k 34k 10k 30k 32k 32k 35k 37k 35k 39k 30k 31k 41k 13k 18k 30k 26k 34k 32k 15k 2k 11k 18k 24k <1k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (42k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project
Buy this chip

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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