Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

Frequency Counter SSD1306 OLED

385 · Other digital · 1 × 2 tiles

by Pawel Sitarz (embelon)

Layout render of Frequency Counter SSD1306 OLED

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		10k (13% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		30k (40% of buffer maximum)
Core covered by logic27%
Transistor density
transistors per mm²		239k average, 317k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Simple Frequency Counter displaying result on SSD1306 SPI OLED

Source repository Its page on Tiny TapeoutBuy this chip

Size347 × 325 µm (0.113 mm²)
Macrott_um_frequency_counter
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles1 × 2 at column 3, row 2 of the tile grid
Mux address385
LanguageSystemVerilog
Clock1 MHz
Built withLibreLane 2.4.2, open_pdks 0fe599b2afb6
Transistors27,576
Logic cells1,157 + 3,114 filler and tap cells
Libraries 7t-5V (1k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

27%
66%
  • Logic cells 0.03 mm² (27%)
  • Filler and tap cells 0.08 mm² (66%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 128D flip-flop (1 bit storage)
nand2_17t-5V 1092-input NAND gate
nor2_17t-5V 1042-input NOR gate
aoi21_17t-5V 77AND-OR-Invert compound gate
clkinv_17t-5V 76Clock inverter
oai21_17t-5V 74OR-AND-Invert compound gate
nand3_17t-5V 423-input NAND gate
and2_17t-5V 322-input AND gate
xor2_17t-5V 322-input XOR gate
aoi22_17t-5V 30AND-OR-Invert (2x2 inputs)

Logic density map

0 logic cells, 2,031 transistors 0 logic cells, 2,128 transistors 0 logic cells, 2,105 transistors 0 logic cells, 882 transistors 6 logic cells, 2,143 transistors 86 logic cells, 2,464 transistors 197 logic cells, 2,795 transistors 80 logic cells, 1,221 transistors 93 logic cells, 2,456 transistors 275 logic cells, 3,218 transistors 234 logic cells, 3,048 transistors 70 logic cells, 1,179 transistors 40 logic cells, 525 transistors 51 logic cells, 640 transistors 22 logic cells, 538 transistors 3 logic cells, 203 transistors Densest SRAM-free 0.1 mm square: 300 logic cells 0 0 0 1k 9k 20k 9k 27k 23k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (30k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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