Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition

Simple RISC-V

359 · RISC-V and CPUs · 4 × 2 tiles

by kinako71-2

Layout render of Simple RISC-V

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		23k (30% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		33k (43% of buffer maximum)
Core covered by logic78%
Transistor density
transistors per mm²		320k average, 346k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

Simple RISC-V based on the university lecture

Source repository Its page on Tiny TapeoutBuy this chip

Size1440 × 325 µm (0.469 mm²)
Macrott_um_simple_riscv
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.2
Tiles4 × 2 at column 7, row 15 of the tile grid
Mux address359
LanguageVerilog
Built withLibreLane 3.0.0.dev45, open_pdks 8afc8346a57f
Transistors152,245
Logic cells11,000 + 11,807 filler and tap cells
Libraries 7t-5V (11k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

78%
18%
  • Logic cells 0.37 mm² (78%)
  • Filler and tap cells 0.09 mm² (18%)
  • Other 0.02 mm² (4%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1,5572-input NAND gate
oai21_17t-5V 1,338OR-AND-Invert compound gate
dffnq_47t-5V 1,216D flip-flop (falling edge, 4x drive)
buf_47t-5V 721Buffer (4x drive)
mux2_27t-5V 5882-input multiplexer (2x drive)
aoi21_17t-5V 515AND-OR-Invert compound gate
buf_27t-5V 511Buffer (2x drive)
nor2_17t-5V 3802-input NOR gate
buf_87t-5V 339Buffer (8x drive)
dffnq_17t-5V 320D flip-flop (falling edge)

Logic density map

130 logic cells, 2,814 transistors 200 logic cells, 3,287 transistors 268 logic cells, 3,226 transistors 271 logic cells, 3,195 transistors 283 logic cells, 3,164 transistors 242 logic cells, 3,235 transistors 268 logic cells, 3,342 transistors 268 logic cells, 3,286 transistors 260 logic cells, 3,418 transistors 270 logic cells, 3,220 transistors 294 logic cells, 3,150 transistors 253 logic cells, 2,899 transistors 222 logic cells, 3,398 transistors 218 logic cells, 3,326 transistors 97 logic cells, 1,063 transistors 209 logic cells, 3,219 transistors 207 logic cells, 3,564 transistors 247 logic cells, 3,498 transistors 264 logic cells, 3,418 transistors 277 logic cells, 3,513 transistors 278 logic cells, 3,530 transistors 256 logic cells, 3,547 transistors 270 logic cells, 3,490 transistors 281 logic cells, 3,515 transistors 239 logic cells, 3,509 transistors 274 logic cells, 3,200 transistors 230 logic cells, 3,046 transistors 246 logic cells, 3,679 transistors 164 logic cells, 3,611 transistors 27 logic cells, 1,071 transistors 191 logic cells, 3,129 transistors 225 logic cells, 3,453 transistors 246 logic cells, 3,483 transistors 243 logic cells, 3,517 transistors 259 logic cells, 3,426 transistors 264 logic cells, 3,372 transistors 264 logic cells, 3,374 transistors 251 logic cells, 3,402 transistors 287 logic cells, 3,540 transistors 255 logic cells, 3,371 transistors 272 logic cells, 3,268 transistors 228 logic cells, 3,129 transistors 172 logic cells, 3,223 transistors 111 logic cells, 3,263 transistors 0 logic cells, 786 transistors 33 logic cells, 552 transistors 46 logic cells, 649 transistors 79 logic cells, 717 transistors 69 logic cells, 687 transistors 59 logic cells, 664 transistors 54 logic cells, 653 transistors 54 logic cells, 677 transistors 54 logic cells, 652 transistors 69 logic cells, 690 transistors 74 logic cells, 683 transistors 54 logic cells, 639 transistors 63 logic cells, 655 transistors 5 logic cells, 489 transistors 6 logic cells, 499 transistors 0 logic cells, 170 transistors Densest SRAM-free 0.1 mm square: 328 logic cells 13k 20k 27k 27k 28k 24k 27k 27k 26k 27k 29k 25k 22k 22k 21k 21k 25k 26k 28k 28k 26k 27k 28k 24k 27k 23k 25k 16k 19k 22k 25k 24k 26k 26k 26k 25k 29k 25k 27k 23k 17k 11k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (33k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

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Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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