Tiny Tapeout GF 0.2 · Die TTPG on wafer.space Run 1: the power-gated edition
Register bank accessible through SPI and I2C
581 · Other digital · 1 × 1 tile
by Caio Alonso da Costa · repository @calonso88
Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
897 logic cells: too few for density figures, which are given for projects of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.
Register bank accessible through SPI and I2C
Source repository Its page on Tiny TapeoutBuy this chip
| Size | 347 × 161 µm (0.056 mm²) |
|---|---|
| Macro | tt_um_calonso88_spi_i2c_reg_bank |
| Files | documentation · licence · layout and netlist in Tiny Tapeout GF 0.2 |
| Tiles | 1 × 1 at column 6, row 0 of the tile grid |
| Mux address | 581 |
| Language | Verilog |
| Clock | 50 MHz |
| Built with | LibreLane 2.4.2, open_pdks 0fe599b2afb6 |
| Transistors | 15,079 |
| Logic cells | 897 + 1,750 filler and tap cells |
| Libraries | 7t-5V (897) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this project's area splits between logic cells, filler and tap cells and other.
- Logic cells 0.03 mm² (51%)
- Filler and tap cells 0.02 mm² (42%)
- Other 4,033 µm² (7%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| dffrnq_1 | 7t-5V | 150 | D flip-flop with reset |
| nand2_1 | 7t-5V | 129 | 2-input NAND gate |
| oai21_1 | 7t-5V | 76 | OR-AND-Invert compound gate |
| mux2_2 | 7t-5V | 44 | 2-input multiplexer (2x drive) |
| aoi21_1 | 7t-5V | 42 | AND-OR-Invert compound gate |
| clkinv_1 | 7t-5V | 39 | Clock inverter |
| nor2_1 | 7t-5V | 38 | 2-input NOR gate |
| nand3_1 | 7t-5V | 27 | 3-input NAND gate |
| and2_1 | 7t-5V | 24 | 2-input AND gate |
| buf_2 | 7t-5V | 21 | Buffer (2x drive) |
Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.