Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
40 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
In this project, we include various floating-gate and non-floating gate standard cells for characterization.
These include:
3 Various charge pumps,
4x2 array of indirectly programmed floating gates,
2 transconductance amplifiers,
1 floating gate characterization cell,
NFET & PFET characterization cells
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.01 mm² inside the pad ring
the project template's, 442 µm in from each edge |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot D2 |
| Bond pads | 72 |
| Transistors | 20,808 |
| Logic cells | 40 + 10 filler and tap cells |
| Libraries | 7t-5V (40) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
The repository has no licence file |
|---|---|
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit 8c360e2ad484. |
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2026-07-15, gf180mcu-precheck 1.7.2 (from its image)
Passed latest re-run, 2026-08-03, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 3.3 V | 24 custom transistors |
|---|---|
| 5 V | 7t-5V standard cells, 16 custom transistors |
| 6 V | 96 custom transistors |
| Gate oxides | Thin (3.3 V) and thick (5 V/6 V) in the design itself |
| MIM capacitors | 12 (19,200 µm², between Metal4 and Metal5) |
| Deep N-well | 12 (463 µm²) |
| Schottky diodes | 12 (190 µm²) |
| I/O library | gf180mcu_fd_io (740 cells) |
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. 0000 was accepted on this check, and has been checked again since with newer rules.
All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-15.
Every step, and the latest re-run
| Step | Accepted on check 677, 2026-07-15, initial, gf180mcu-precheck 1.7.2 (from its image) PDK open_pdks 1.0.604, LibreLane 5fe3db1 | Latest re-run check 786, 2026-08-03, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | passed | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | passed | passed |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 0 | 0 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.