wafer.space Run 1

WS-Multi

AS03 · Multi-project die · 1 × 1 slot

Layout render of WS-Multi

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		7k (9% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		4k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		21k (28% of buffer maximum)
Core covered by logic19%
Transistor density
transistors per mm²		188k average, 272k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Multi-project die

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot D5 AS03 on the reticle
Bond pads74
Transistors2,430,570
Logic cells86,629 + 302,626 filler and tap cells
Libraries 7t-5V (81k), AS extra 7t-5V (4k), 9t-5V (2k)
SRAMNo SRAM

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.5
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit ef1e1212213b.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2026-01-04, gf180mcu-precheck 1.5.5 (from its image)
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, AS extra 7t-5V standard cells, 9t-5V standard cells, 990 custom transistors
Gate oxidesThick only (5 V/6 V) in the design itself
High-resistance poly resistors319 (1,621 µm²)
I/O librarygf180mcu_fd_io (1127 cells), gf180mcu_ws_io (13 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

12%
36%
16%
36%
  • Logic cells 2.41 mm² (12%)
  • Filler and tap cells 7.33 mm² (36%)
  • Other 3.17 mm² (16%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 9,9172-input NAND gate
dlyb_17t-5V 4,879Delay buffer
nor2_17t-5V 4,8152-input NOR gate
oai21_17t-5V 4,728OR-AND-Invert compound gate
aoi22_17t-5V 4,564AND-OR-Invert (2x2 inputs)
dffq_17t-5V 3,775D flip-flop (1 bit storage)
xor2_17t-5V 3,6852-input XOR gate
clkinv_17t-5V 3,525Clock inverter
aoi21_17t-5V 3,490AND-OR-Invert compound gate
dfxtn_2AS extra 7t-5V 2,436D flip-flop (falling edge, 2x drive)

Logic density map

1,022 logic cells, 74,964 transistors 2,703 logic cells, 134,483 transistors 681 logic cells, 106,962 transistors 0 logic cells, 51,810 transistors 2,120 logic cells, 124,524 transistors 9,051 logic cells, 243,417 transistors 7,867 logic cells, 226,780 transistors 5,541 logic cells, 112,935 transistors 5,025 logic cells, 117,079 transistors 12,186 logic cells, 231,305 transistors 12,997 logic cells, 233,588 transistors 8,479 logic cells, 117,810 transistors 0 logic cells, 36,471 transistors 2,776 logic cells, 120,607 transistors 1,375 logic cells, 81,258 transistors 0 logic cells, 24,218 transistors 1,384 logic cells, 68,958 transistors 8,530 logic cells, 159,877 transistors 4,892 logic cells, 102,986 transistors 0 logic cells, 59,701 transistors 0 logic cells, 176 transistors 0 logic cells, 255 transistors 0 logic cells, 255 transistors 0 logic cells, 151 transistors Densest SRAM-free mm²: 21,295 logic cells 1k 3k 1k 0 2k 9k 8k 6k 5k 12k 13k 8k 0 3k 1k 0 1k 9k 5k 0

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (21k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Avalon Semiconductors' retro-computing family has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Tiny Tapeout 2 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
  2. Dec 2022 · Google GFMPW-0 105A AS2650 — Caravel chip, a Signetics 2650 8-bit CPU replica
  3. Apr 2023 · Tiny Tapeout 3 Avalon Semiconductors '5401' 4-bit Microprocessor — 1 × 1 tile, a 4-bit microprocessor Avalon Semiconductors 'TBB1143' Programmable Sound Generator — 1 × 1 tile, a programmable sound generator
  4. Dec 2025 · wafer.space Run 1 AS03 WS-Multi — 1 × 1 slot, a multi-project die: 6502 and SID replicas, an RV32IMA core, a DRAM controller and more
  5. Jul 2026 · wafer.space Run 2 AS04 Multi-Project die using 3.3V SCL — 1 × 1 slot, the multi-project die again, on 3.3 V standard cells

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 105A 1 × 17t-5V 5 V/6 V only 4,846 1k 5k none
wafer.space Run 1 · AS03 1 × 1mixed 5 V/6 V only 86,629 7k 21k none
wafer.space Run 2 · AS04 1 × 1AS 7t-3.3V 3.3 V only 87,322 7k 19k none

From Tiny Tapeout tiles to a die of its own

Avalon Semiconductors' retro-computing family was tried on Tiny Tapeout 2 and a Google shuttle, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of WS-Multi by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. AS03 was accepted on this check.

All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-04.

Every step
StepAccepted on, and latest
check 243, 2026-01-04, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e
KLayout.ReadLayoutpassed
KLayout.CheckTopLevelpassed
KLayout.CheckSizepassed
KLayout.GenerateIDpassed
KLayout.Densitypassed
Checker.KLayoutDensitypassed
KLayout.ZeroAreaPolygonspassed
Checker.KLayoutZeroAreaPolygonspassed
KLayout.Antennapassed
Checker.KLayoutAntennapassed
Magic.DRCpassed
Checker.MagicDRCpassed
KLayout.DRCpassed
Checker.KLayoutDRCpassed
KLayout.WriteLayoutpassed
KLayout DRC errors0
Magic DRC errors (advisory)0
Filessteps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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