wafer.space Run 1

Cloneless1

2975 · Security · 1 × 1 slot

Layout render of Cloneless1

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		25k (32% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		16k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		32k (42% of buffer maximum)
Core covered by logic56%
Transistor density
transistors per mm²		279k average, 293k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Cloneless1 is a cryptographic ASIC that implements a physically secure block cipher instance with tamper-resistant long-term secret via physically unclonable function and leakage-resilient secret sharing.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements2 on the reticle, in slots A2, B2 2975 on the reticle
Bond pads32
Transistors3,596,371
Logic cells316,440 + 463,577 filler and tap cells
Libraries 7t-5V (316k)
SRAMNo SRAM

Submission

LicenceGPL-3.0-only declared
Repository: GPL-3.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.5
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit fdc35ddf99bf.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-19, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1373 cells), gf180mcu_ws_io (17 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

36%
26%
36%
  • Logic cells 7.19 mm² (36%)
  • Filler and tap cells 5.28 mm² (26%)
  • Other 0.43 mm² (2%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 54,8302-input NAND gate
xor2_17t-5V 51,5332-input XOR gate
nor2_17t-5V 28,8202-input NOR gate
xnor2_17t-5V 18,7832-input XNOR gate
oai21_17t-5V 18,654OR-AND-Invert compound gate
clkinv_17t-5V 18,206Clock inverter
aoi21_17t-5V 17,686AND-OR-Invert compound gate
dlyb_17t-5V 11,880Delay buffer
dffq_17t-5V 11,507D flip-flop (1 bit storage)
and2_17t-5V 10,2592-input AND gate

Logic density map

0 logic cells, 72,854 transistors 13,646 logic cells, 159,648 transistors 14,091 logic cells, 156,934 transistors 2,902 logic cells, 70,382 transistors 11,613 logic cells, 152,040 transistors 27,707 logic cells, 279,567 transistors 30,952 logic cells, 291,846 transistors 10,630 logic cells, 133,802 transistors 14,389 logic cells, 166,785 transistors 28,395 logic cells, 288,449 transistors 27,673 logic cells, 257,401 transistors 13,630 logic cells, 139,580 transistors 12,153 logic cells, 151,705 transistors 29,438 logic cells, 274,174 transistors 28,696 logic cells, 289,780 transistors 10,412 logic cells, 143,534 transistors 2,668 logic cells, 94,192 transistors 21,354 logic cells, 202,316 transistors 15,913 logic cells, 192,242 transistors 178 logic cells, 78,175 transistors 0 logic cells, 204 transistors 0 logic cells, 292 transistors 0 logic cells, 292 transistors 0 logic cells, 177 transistors Densest SRAM-free mm²: 31,548 logic cells 0 14k 14k 3k 12k 28k 31k 11k 14k 28k 28k 14k 12k 29k 29k 10k 3k 21k 16k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (32k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. 2975 was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-19.

Every step, and the latest re-run
StepAccepted on
check 197, 2025-12-19, retry, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 708, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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