wafer.space Run 1

FA25_Engn2912e_Saligane_Brown

BRWN · Other digital · 1 × 1 slot

Layout render of FA25_Engn2912e_Saligane_Brown

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		<1k (<1% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		<1k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		3k (3% of buffer maximum)
Core covered by logic1%
Transistor density
transistors per mm²		50k average, 119k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

FA25 ENGN2912e@Brown Course Project

Die photographBonding results

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot E4 BRWN on the reticle
Bond pads74
Transistors649,130
Logic cells4,379 + 64,895 filler and tap cells
Libraries 7t-5V (4k)
SRAMNo SRAM

Submission

Licenceproprietary declared
No public repository
Chip-on-boardNot selected at submission · bonding results
PrecheckPassed the check it was accepted on, 2025-12-18, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-07-30, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V67,982 custom transistors
5 V7t-5V standard cells
Gate oxidesThin (3.3 V) and thick (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and pad ring.

13%
50%
36%
  • Logic cells 0.16 mm² (1%)
  • Filler and tap cells 2.68 mm² (13%)
  • Other 10.07 mm² (50%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffrnq_17t-5V 490D flip-flop with reset
dffrnq_1_07t-5V 422D flip-flop with reset
mux2_2_07t-5V 3052-input multiplexer (2x drive)
clkinv_17t-5V 294Clock inverter
clkinv_1_07t-5V 248Clock inverter
mux2_27t-5V 1792-input multiplexer (2x drive)
nor2_17t-5V 1752-input NOR gate
oai21_17t-5V 173OR-AND-Invert compound gate
dlyb_17t-5V 172Delay buffer
aoi21_17t-5V 138AND-OR-Invert compound gate

Logic density map

0 logic cells, 4,474 transistors 0 logic cells, 3,635 transistors 0 logic cells, 3,685 transistors 0 logic cells, 4,364 transistors 0 logic cells, 2,675 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 3,634 transistors 0 logic cells, 2,827 transistors 0 logic cells, 0 transistors 0 logic cells, 7,062 transistors 12 logic cells, 17,448 transistors 702 logic cells, 46,437 transistors 251 logic cells, 99,187 transistors 91 logic cells, 106,997 transistors 227 logic cells, 36,912 transistors 1,329 logic cells, 57,671 transistors 308 logic cells, 107,645 transistors 422 logic cells, 104,301 transistors 1,037 logic cells, 39,346 transistors 0 logic cells, 160 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors Densest SRAM-free mm²: 2,590 logic cells 0 0 0 0 0 0 0 0 0 0 0 <1k 1k <1k <1k <1k 1k <1k <1k 1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (3k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of FA25_Engn2912e_Saligane_Brown by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Chip-on-board bonding

Wire bonding results for BRWN

From the chip-on-board results page.

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. BRWN was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-18.

Every step, and the latest re-run
StepAccepted on
check 188, 2025-12-18, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 703, 2026-07-30, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCadvisory warningadvisory warning
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)6,5778
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

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