wafer.space Run 1

BreakingTTAPs

BTAP · RISC-V and CPUs · 1 × 1 slot

Layout render of BreakingTTAPs

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		3k (6% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		2k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		21k (35% of buffer maximum)
Core covered by logic9%
Transistor density
transistors per mm²		168k average, 224k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Transport Triggered Architecture processor

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements2 on the reticle, in slots A5, B5 BTAP on the reticle
Bond pads74
Transistors2,166,150
Logic cells43,225 + 156,483 filler and tap cells
Libraries 9t-5V (43k)
SRAM28 macros, 106,496 bits

Submission

LicenceCERN-OHL-S-2.0 declared
Repository: Apache-2.0 in LICENSE, not the declared licence
Templatewafer-space/gf180mcu-project-template 1.3.5
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 8f357d6ffb79.The template release named above is the one whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.6).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-25, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V9t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

28%
27%
36%
  • Logic cells 1.22 mm² (6%)
  • SRAM 5.61 mm² (28%)
  • Filler and tap cells 5.50 mm² (27%)
  • Other 0.59 mm² (3%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_19t-5V 8,7832-input NAND gate
buf_29t-5V 4,001Buffer (2x drive)
clkbuf_49t-5V 2,036Clock buffer (4x drive)
clkinv_19t-5V 2,005Clock inverter
nor2_19t-5V 1,9972-input NOR gate
aoi21_19t-5V 1,969AND-OR-Invert compound gate
nand3_19t-5V 1,8563-input NAND gate
clkbuf_29t-5V 1,746Clock buffer (2x drive)
dffq_19t-5V 1,638D flip-flop (1 bit storage)
dlyb_19t-5V 1,425Delay buffer

Logic density map

1 logic cells, 49,926 transistors, 21% SRAM 46 logic cells, 86,882 transistors, 41% SRAM 24 logic cells, 85,299 transistors, 43% SRAM 28 logic cells, 51,220 transistors 6 logic cells, 88,294 transistors, 46% SRAM 12,331 logic cells, 207,012 transistors, <1% SRAM 2,613 logic cells, 162,050 transistors, 38% SRAM 12 logic cells, 85,178 transistors, 5% SRAM 140 logic cells, 79,132 transistors, 36% SRAM 16,178 logic cells, 206,966 transistors, 14% SRAM 8,976 logic cells, 176,936 transistors, 38% SRAM 392 logic cells, 86,225 transistors, 5% SRAM 30 logic cells, 89,158 transistors, 15% SRAM 1,665 logic cells, 160,134 transistors, 47% SRAM 587 logic cells, 146,301 transistors, 80% SRAM 50 logic cells, 76,816 transistors, 25% SRAM 12 logic cells, 68,190 transistors, 9% SRAM 64 logic cells, 102,840 transistors, 45% SRAM 60 logic cells, 102,122 transistors, 46% SRAM 10 logic cells, 54,623 transistors, 14% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram256x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram256x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram256x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram256x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 Densest SRAM-free mm²: 20,600 logic cells <1k <1k <1k <1k <1k 12k 3k <1k <1k 16k 9k <1k <1k 2k 1k <1k <1k <1k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (21k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram256x8m8wm14 2,048
gf180mcu_fd_ip_sram__sram512x8m8wm124 4,096

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of BreakingTTAPs by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. BTAP was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-25.

Every step, and the latest re-run
StepAccepted on
check 208, 2025-12-25, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 719, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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