wafer.space Run 1

FazyRV Hachure

CAFE · RISC-V and CPUs · 1 × 1 slot

Layout render of FazyRV Hachure

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		8k (10% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		5k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²		21k (28% of buffer maximum)
Core covered by logic26%
Transistor density
transistors per mm²		226k average, 292k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

FazyRV Hachure is a System on Chip that integrates seven different variants of the bit-serial FazyRV RISC-V core in one chip for testing and research purposes.

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot G5 CAFE on the reticle
Bond pads74
Transistors2,919,680
Logic cells100,546 + 266,996 filler and tap cells
Libraries 7t-5V (101k)
SRAM20 macros, 81,920 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.1 or 1.3.2
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 51047e6350b7.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2026-01-04, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

17%
21%
23%
36%
  • Logic cells 3.37 mm² (17%)
  • SRAM 4.19 mm² (21%)
  • Filler and tap cells 4.68 mm² (23%)
  • Other 0.68 mm² (3%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
dffq_17t-5V 18,190D flip-flop (1 bit storage)
mux2_27t-5V 16,5982-input multiplexer (2x drive)
buf_27t-5V 10,031Buffer (2x drive)
dlyb_17t-5V 8,991Delay buffer
nand2_17t-5V 5,4562-input NAND gate
buf_47t-5V 5,045Buffer (4x drive)
aoi22_17t-5V 4,760AND-OR-Invert (2x2 inputs)
aoi21_17t-5V 3,407AND-OR-Invert compound gate
nor2_17t-5V 2,7532-input NOR gate
oai21_17t-5V 2,681OR-AND-Invert compound gate

Logic density map

2,931 logic cells, 82,439 transistors 7,596 logic cells, 152,429 transistors 8,024 logic cells, 154,450 transistors 3,910 logic cells, 74,721 transistors 5,338 logic cells, 144,842 transistors 20,811 logic cells, 292,781 transistors 15,233 logic cells, 295,484 transistors 100 logic cells, 111,907 transistors 4,762 logic cells, 124,268 transistors, 19% SRAM 10,370 logic cells, 237,884 transistors, 30% SRAM 9,904 logic cells, 242,830 transistors, 29% SRAM 3,175 logic cells, 108,532 transistors, 18% SRAM 175 logic cells, 87,719 transistors, 38% SRAM 3,609 logic cells, 168,259 transistors, 60% SRAM 3,887 logic cells, 181,673 transistors, 59% SRAM 22 logic cells, 81,585 transistors, 37% SRAM 95 logic cells, 69,148 transistors, 26% SRAM 331 logic cells, 116,539 transistors, 41% SRAM 261 logic cells, 127,098 transistors, 40% SRAM 12 logic cells, 64,254 transistors, 25% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 151 transistors gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 Densest SRAM-free mm²: 21,486 logic cells 3k 8k 8k 4k 5k 21k 15k <1k 5k 10k 10k 3k <1k 4k 4k <1k <1k <1k <1k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (21k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram512x8m8wm120 4,096

FazyRV has been made on 3 shuttles since Apr 2024. Every version, oldest first, with this one in bold:

  1. Apr 2024 · Tiny Tapeout 6 FazyRV-ExoTiny — 2 × 2 tiles, FazyRV-ExoTiny
  2. Nov 2024 · Tiny Tapeout IHP 0.2 FazyRV-ExoTiny — 3 × 2 tiles, FazyRV-ExoTiny
  3. Dec 2025 · wafer.space Run 1 CAFE FazyRV Hachure — 1 × 1 slot, FazyRV Hachure

Tiny Tapeout tile Google shuttle wafer.space die

From Tiny Tapeout tiles to a die of its own

FazyRV began as tiles on Tiny Tapeout 6, and now has a die of its own on wafer.space Run 1.

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of FazyRV Hachure by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. CAFE was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2026-01-04.

Every step, and the latest re-run
StepAccepted on
check 241, 2026-01-04, initial, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 731, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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