Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 11k
(19% of buffer maximum) over the 12.92 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 7k
over all 19.65 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 13k (21% of buffer maximum) |
| Core covered by logic | 35% |
| Transistor density transistors per mm² | 209k average, 228k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Eight-core chess move generator.
Source repository Die photograph
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 12.92 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 19.65 mm² (the die less its 26 µm seal ring) |
| Placements | 1 on the reticle, in slot F3 |
| Bond pads | 74 |
| Transistors | 2,701,676 |
| Logic cells | 145,076 + 406,519 filler and tap cells |
| Libraries | 9t-5V (145k) |
| SRAM | No SRAM |
Submission
| Licence | Apache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.3.1 or 1.3.2 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit b73046558e5a.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4). |
| Chip-on-board | Not selected at submission |
| Precheck | Passed
the check it was accepted on, 2025-12-11
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 9t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells) |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and pad ring.
- Logic cells 4.47 mm² (22%)
- Filler and tap cells 8.43 mm² (42%)
- Other 0.02 mm² (<1%)
- Pad ring 7.20 mm² (36%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 9t-5V | 20,053 | 2-input NAND gate |
| nor2_1 | 9t-5V | 11,610 | 2-input NOR gate |
| mux2_1 | 9t-5V | 11,415 | 2-input multiplexer |
| oai21_1 | 9t-5V | 7,132 | OR-AND-Invert compound gate |
| aoi21_1 | 9t-5V | 6,916 | AND-OR-Invert compound gate |
| buf_1 | 9t-5V | 5,343 | Buffer |
| buf_2 | 9t-5V | 5,031 | Buffer (2x drive) |
| buf_4 | 9t-5V | 4,801 | Buffer (4x drive) |
| nand3_1 | 9t-5V | 4,697 | 3-input NAND gate |
| clkinv_1 | 9t-5V | 4,429 | Clock inverter |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (13k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
How this design grew
Chess move generator has been made on 3 shuttles since Jun 2024. Every version, oldest first, with this one in bold:
- Jun 2024 · Tiny Tapeout 7 Chess — 3 × 2 tiles
- Nov 2024 · Tiny Tapeout IHP 0.2 Chess — 3 × 2 tiles
- Dec 2025 · wafer.space Run 1 CHES chess-move-generator — 1 × 1 slot
Tiny Tapeout tile Google shuttle wafer.space die
From Tiny Tapeout tiles to a die of its own
Chess move generator began as tiles on Tiny Tapeout 7, and now has a die of its own on wafer.space Run 1.
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. CHES was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-11.
Every step, and the latest re-run
| Step | Accepted on check 88, 2025-12-11, initial | Latest re-run check 767, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | not in this flow | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | advisory warning | advisory warning |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 14 | 14 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.