Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless
Synchronous modulator
6E0D · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | <1k (<1% of buffer maximum) |
|---|---|
| Densest mm² logic cells per mm² | 2k (2% of buffer maximum) |
| Core covered by logic | <1% |
| Transistor density transistors per mm² | 2k average, 16k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Synchronous modulator, part of a PhD project at CINVESTAV Guadalajara.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle, in slot B8 |
| Bond pads | 63 |
| Transistors | 15,966 |
| Logic cells | 1,558 + 7,532 filler and tap cells |
| Libraries | 7t-5V (2k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and outside the user area.
- Logic cells 0.03 mm² (<1%)
- Filler and tap cells 0.04 mm² (<1%)
- Other 8.92 mm² (44%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 185 | Clock buffer |
| buf_1 | 7t-5V | 148 | Buffer |
| nand2_1 | 7t-5V | 141 | 2-input NAND gate |
| oai21_1 | 7t-5V | 99 | OR-AND-Invert compound gate |
| aoi21_1 | 7t-5V | 95 | AND-OR-Invert compound gate |
| nor2_1 | 7t-5V | 91 | 2-input NOR gate |
| xor2_1 | 7t-5V | 58 | 2-input XOR gate |
| and2_1 | 7t-5V | 46 | 2-input AND gate |
| clkbuf_2 | 7t-5V | 46 | Clock buffer (2x drive) |
| nand3_1 | 7t-5V | 44 | 3-input NAND gate |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (2k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.