Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless
TestAsyncTrimux
B22E · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
89 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Test circuit for a 3-rail asynchronous ternary selector, designed in Wokwi. By Alexander Shabarshin.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle, in slot A6 |
| Bond pads | 63 |
| Transistors | 82,220 |
| Logic cells | 89 + 10,989 filler and tap cells |
| Libraries | 7t-5V (89) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this design's area splits between filler and tap cells, other and outside the user area.
- Filler and tap cells 0.38 mm² (2%)
- Other 8.62 mm² (43%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 16 | Clock buffer |
| nor2_1 | 7t-5V | 16 | 2-input NOR gate |
| aoi21_1 | 7t-5V | 12 | AND-OR-Invert compound gate |
| clkbuf_3 | 7t-5V | 12 | Clock buffer (3x drive) |
| dlyb_1 | 7t-5V | 12 | Delay buffer |
| nor3_1 | 7t-5V | 6 | 3-input NOR gate |
| nor3_2 | 7t-5V | 4 | 3-input NOR gate (2x drive) |
| clkinv_1 | 7t-5V | 2 | Clock inverter |
| dlyc_1 | 7t-5V | 2 | Delay buffer |
| nand2_1 | 7t-5V | 2 | 2-input NAND gate |