Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

Signed 8-bit multiplier

A3A3 · Other digital · 1 × 1 slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Signed 8-bit multiplier, alongside the VGA clock demo.

Source repository

Die	3.93 × 5.12 mm (20.1 mm²)
Core area	9.00 mm² inside the pad ring its user_project_wrapper cell
Placements	1 on the reticle, in slot B2
Bond pads	63
Transistors	16,376
Logic cells	0 + 2,385 filler and tap cells
SRAM	No SRAM

Where the area went

How this design's area splits between filler and tap cells, other and outside the user area.

44%

55%

Filler and tap cells 0.08 mm² (<1%)
Other 8.92 mm² (44%)
Outside the user area 11.12 mm² (55%)

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wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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