Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

One-hot FABulous FPGA

56C6 · FPGA · 1 × 1 slot

Layout render of One-hot FABulous FPGA

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		4k (5% of buffer maximum)
Densest mm²
logic cells per mm²		5k (7% of buffer maximum)
Core covered by logic11%
Transistor density
transistors per mm²		147k average, 142k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

FABulous FPGA test on GF180 with a custom one-hot SRAM and transmission gate element for routing.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot C2 56C6 on the reticle
Bond pads63
Transistors1,319,690
Logic cells32,037 + 689,411 filler and tap cells
Libraries 7t-5V (32k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, 297,328 custom transistors
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and outside the user area.

27%
13%
55%
  • Logic cells 1.01 mm² (5%)
  • Filler and tap cells 5.37 mm² (27%)
  • Other 2.61 mm² (13%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
bufz_17t-5V 8,496Tri-state buffer
buf_17t-5V 7,411Buffer
latq_17t-5V 5,640Latch (level-sensitive)
mux2_27t-5V 1,8482-input multiplexer (2x drive)
buf_47t-5V 1,565Buffer (4x drive)
inv_47t-5V 1,536Inverter (4x drive)
mux4_17t-5V 1,4404-input multiplexer
buf_87t-5V 1,225Buffer (8x drive)
nor2_17t-5V 6042-input NOR gate
dffq_17t-5V 515D flip-flop (1 bit storage)

Logic density map

0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 150 logic cells, 29,917 transistors 612 logic cells, 50,420 transistors 798 logic cells, 51,542 transistors 170 logic cells, 26,061 transistors 1,649 logic cells, 79,563 transistors 4,209 logic cells, 137,465 transistors 3,991 logic cells, 135,440 transistors 1,599 logic cells, 69,443 transistors 1,928 logic cells, 79,799 transistors 5,126 logic cells, 139,605 transistors 4,849 logic cells, 137,590 transistors 1,871 logic cells, 69,302 transistors 660 logic cells, 57,881 transistors 1,929 logic cells, 102,778 transistors 1,830 logic cells, 103,414 transistors 666 logic cells, 49,470 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors Densest SRAM-free mm²: 5,395 logic cells 0 0 0 0 <1k 1k 1k <1k 2k 4k 4k 2k 2k 5k 5k 2k 1k 2k 2k 1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (5k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

FABulous FPGA has been made on 9 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Google GFMPW-0 56C6 One-hot FABulous FPGA — Caravel chip, a one-hot FPGA built with the FABulous framework
  2. Dec 2025 · wafer.space Run 1 MOLE FABulous FPGA — 1 × 1 slot
  3. Mar 2026 · Tiny Tapeout IHP 26a Tiny FABulous FPGA — 8 × 4 tiles
  4. May 2026 · Tiny Tapeout SKY 26a Tiny FABulous FPGA — 8 × 4 tiles
  5. May 2026 · Tiny Tapeout SKY 26b Tiny FABulous FPGA — 8 × 4 tiles
  6. Jun 2026 · Tiny Tapeout GF 0.3 Tiny FABulous FPGA — 4 × 4 tiles Tiny FABulous FPGA (3.3V version) — 4 × 4 tiles, 3.3 V version
  7. Jul 2026 · wafer.space Run 2 MOLE FABulous FPGA — 1 × 1 slot
  8. Sep 2026 · Tiny Tapeout SKY 26c Tiny FABulous FPGA — 8 × 4 tiles
  9. Sep 2026 · Tiny Tapeout IHP 26b Tiny FABulous FPGA — 6 × 4 tiles

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 56C6 1 × 17t-5V 5 V/6 V only 32,037 4k 5k none
wafer.space Run 1 · MOLE 1 × 17t-5V 5 V/6 V only 203,757 16k 27k 6 macros
wafer.space Run 2 · MOLE 1 × 1AS 7t-3.3V 3.3 V only 211,813 16k 24k 13 macros

Parts of this design are on Tiny Tapeout chips too

Tiny Tapeout puts many small designs on one chip, so trying out a block costs a fraction of a whole die: a cheap way to test one piece of a bigger design before it goes on a die of its own.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

Reserve a slot
Start with Tiny Tapeout
← 4F9E MCU for solar power All projects TestFlipFlops 58D2 →