Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

Tiny FABulous FPGA

102 · FPGA · 4 × 4 tiles

by Leo Moser

Layout render of Tiny FABulous FPGA

Rendered from the layout at 0.90 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		18k (24% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		32k (42% of buffer maximum)
Core covered by logic58%
Transistor density
transistors per mm²		255k average, 264k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A tiny FABulous FPGA fabric, ready for use with Yosys and nextpnr.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size1440 × 737 µm (1.061 mm²)
Macrott_um_fabulous_gf_0p3
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles4 × 4 at column 7, row 10 of the tile grid
Mux address102
LanguageVerilog
Transistors272,114
Logic cells19,232 + 23,147 filler and tap cells
Libraries 7t-5V (19k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

58%
27%
15%
  • Logic cells 0.62 mm² (58%)
  • Filler and tap cells 0.28 mm² (27%)
  • Other 0.16 mm² (15%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
latq_17t-5V 5,504Latch (level-sensitive)
buf_17t-5V 4,916Buffer
mux4_17t-5V 2,4444-input multiplexer
clkinv_17t-5V 1,035Clock inverter
nand2_17t-5V 8172-input NAND gate
nor2_17t-5V 6382-input NOR gate
mux2_27t-5V 6062-input multiplexer (2x drive)
aoi21_17t-5V 545AND-OR-Invert compound gate
oai21_17t-5V 538OR-AND-Invert compound gate
dffq_17t-5V 339D flip-flop (1 bit storage)

Logic density map

13 logic cells, 2,055 transistors 109 logic cells, 2,379 transistors 179 logic cells, 2,118 transistors 144 logic cells, 2,455 transistors 202 logic cells, 2,111 transistors 125 logic cells, 2,469 transistors 172 logic cells, 2,418 transistors 171 logic cells, 2,115 transistors 145 logic cells, 2,471 transistors 204 logic cells, 2,150 transistors 124 logic cells, 2,404 transistors 171 logic cells, 2,429 transistors 196 logic cells, 2,057 transistors 63 logic cells, 425 transistors 0 logic cells, 0 transistors 0 logic cells, 2,142 transistors 141 logic cells, 2,801 transistors 283 logic cells, 3,060 transistors 269 logic cells, 3,380 transistors 287 logic cells, 3,017 transistors 276 logic cells, 3,413 transistors 264 logic cells, 3,406 transistors 290 logic cells, 3,035 transistors 265 logic cells, 3,404 transistors 272 logic cells, 3,081 transistors 292 logic cells, 3,339 transistors 271 logic cells, 3,396 transistors 242 logic cells, 2,993 transistors 64 logic cells, 649 transistors 0 logic cells, 0 transistors 1 logic cells, 2,143 transistors 116 logic cells, 2,623 transistors 248 logic cells, 2,994 transistors 239 logic cells, 3,350 transistors 241 logic cells, 3,078 transistors 250 logic cells, 3,318 transistors 249 logic cells, 3,441 transistors 256 logic cells, 2,991 transistors 234 logic cells, 3,374 transistors 234 logic cells, 3,174 transistors 254 logic cells, 3,240 transistors 255 logic cells, 3,422 transistors 250 logic cells, 3,053 transistors 57 logic cells, 694 transistors 0 logic cells, 0 transistors 63 logic cells, 2,321 transistors 153 logic cells, 2,719 transistors 259 logic cells, 2,781 transistors 231 logic cells, 3,144 transistors 264 logic cells, 2,754 transistors 237 logic cells, 3,146 transistors 245 logic cells, 3,140 transistors 257 logic cells, 2,761 transistors 229 logic cells, 3,162 transistors 249 logic cells, 2,821 transistors 253 logic cells, 3,070 transistors 242 logic cells, 3,150 transistors 229 logic cells, 2,742 transistors 49 logic cells, 579 transistors 0 logic cells, 0 transistors 24 logic cells, 2,226 transistors 131 logic cells, 2,768 transistors 268 logic cells, 3,030 transistors 255 logic cells, 3,348 transistors 266 logic cells, 3,049 transistors 268 logic cells, 3,377 transistors 249 logic cells, 3,408 transistors 276 logic cells, 3,039 transistors 248 logic cells, 3,382 transistors 256 logic cells, 3,113 transistors 281 logic cells, 3,300 transistors 256 logic cells, 3,392 transistors 255 logic cells, 3,008 transistors 70 logic cells, 656 transistors 0 logic cells, 0 transistors 89 logic cells, 2,482 transistors 166 logic cells, 2,625 transistors 239 logic cells, 2,747 transistors 219 logic cells, 3,087 transistors 218 logic cells, 2,785 transistors 229 logic cells, 3,070 transistors 226 logic cells, 3,162 transistors 235 logic cells, 2,737 transistors 213 logic cells, 3,131 transistors 210 logic cells, 2,887 transistors 235 logic cells, 2,953 transistors 231 logic cells, 3,132 transistors 225 logic cells, 2,770 transistors 41 logic cells, 659 transistors 0 logic cells, 0 transistors 60 logic cells, 2,436 transistors 182 logic cells, 2,606 transistors 235 logic cells, 2,345 transistors 129 logic cells, 2,437 transistors 186 logic cells, 2,105 transistors 214 logic cells, 2,755 transistors 197 logic cells, 2,556 transistors 208 logic cells, 2,289 transistors 193 logic cells, 2,602 transistors 211 logic cells, 2,195 transistors 130 logic cells, 2,197 transistors 94 logic cells, 2,263 transistors 175 logic cells, 1,980 transistors 56 logic cells, 875 transistors 0 logic cells, 213 transistors 0 logic cells, 712 transistors 0 logic cells, 729 transistors 1 logic cells, 738 transistors 4 logic cells, 779 transistors 0 logic cells, 737 transistors 0 logic cells, 736 transistors 0 logic cells, 729 transistors 0 logic cells, 737 transistors 0 logic cells, 736 transistors 0 logic cells, 729 transistors 0 logic cells, 737 transistors 0 logic cells, 729 transistors 0 logic cells, 736 transistors 0 logic cells, 737 transistors 0 logic cells, 279 transistors Densest SRAM-free 0.1 mm square: 320 logic cells 1k 11k 18k 14k 20k 12k 17k 17k 14k 20k 12k 17k 20k 6k 0 14k 28k 27k 29k 28k 26k 29k 26k 27k 29k 27k 24k 6k <1k 12k 25k 24k 24k 25k 25k 26k 23k 23k 25k 25k 25k 6k 6k 15k 26k 23k 26k 24k 24k 26k 23k 25k 25k 24k 23k 5k 2k 13k 27k 25k 27k 27k 25k 28k 25k 26k 28k 26k 25k 7k 9k 17k 24k 22k 22k 23k 23k 23k 21k 21k 23k 23k 22k 4k 6k 18k 23k 13k 19k 21k 20k 21k 19k 21k 13k 9k 17k 6k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (32k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

FABulous FPGA has been made on 9 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Google GFMPW-0 56C6 One-hot FABulous FPGA — Caravel chip, a one-hot FPGA built with the FABulous framework
  2. Dec 2025 · wafer.space Run 1 MOLE FABulous FPGA — 1 × 1 slot
  3. Mar 2026 · Tiny Tapeout IHP 26a Tiny FABulous FPGA — 8 × 4 tiles
  4. May 2026 · Tiny Tapeout SKY 26a Tiny FABulous FPGA — 8 × 4 tiles
  5. May 2026 · Tiny Tapeout SKY 26b Tiny FABulous FPGA — 8 × 4 tiles
  6. Jun 2026 · Tiny Tapeout GF 0.3 Tiny FABulous FPGA — 4 × 4 tiles Tiny FABulous FPGA (3.3V version) — 4 × 4 tiles, 3.3 V version
  7. Jul 2026 · wafer.space Run 2 MOLE FABulous FPGA — 1 × 1 slot
  8. Sep 2026 · Tiny Tapeout SKY 26c Tiny FABulous FPGA — 8 × 4 tiles
  9. Sep 2026 · Tiny Tapeout IHP 26b Tiny FABulous FPGA — 6 × 4 tiles

Tiny Tapeout tile Google shuttle wafer.space die

From a Tiny Tapeout tile to a whole die

FABulous FPGA started as a few tiles on Tiny Tapeout IHP 26a and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2. When your design outgrows its tiles, a whole die on a wafer.space run is the next step.

Reserve a slot on wafer.space Run 3

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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