Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

Serv tri-core (GF180 MPW0 Serv)

6079 · RISC-V and CPUs · 1 × 1 slot

Layout render of Serv tri-core (GF180 MPW0 Serv)

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		2k (3% of buffer maximum)
Densest mm²
logic cells per mm²		12k (16% of buffer maximum)
Core covered by logic6%
Transistor density
transistors per mm²		40k average, 181k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

SERV RISC-V CPUs with a scan chain around the Wishbone bus. By Greg Davill.

Source repository

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot A1 6079 on the reticle
Bond pads63
Transistors359,685
Logic cells17,345 + 96,994 filler and tap cells
Libraries 7t-5V (17k)
SRAM1 macro, 2,048 bits

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and outside the user area.

36%
55%
  • Logic cells 0.50 mm² (2%)
  • SRAM 0.15 mm² (1%)
  • Filler and tap cells 1.02 mm² (5%)
  • Other 7.33 mm² (36%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 3,3172-input NAND gate
dffq_17t-5V 3,070D flip-flop (1 bit storage)
oai21_17t-5V 2,381OR-AND-Invert compound gate
buf_17t-5V 2,107Buffer
dlyb_17t-5V 687Delay buffer
aoi21_17t-5V 646AND-OR-Invert compound gate
clkbuf_17t-5V 614Clock buffer
mux4_17t-5V 5794-input multiplexer
dlyc_17t-5V 479Delay buffer
nor2_17t-5V 4662-input NOR gate

Logic density map

0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 2,303 transistors 2,408 logic cells, 119,050 transistors, 15% SRAM 0 logic cells, 0 transistors 0 logic cells, 0 transistors 82 logic cells, 3,147 transistors 12,266 logic cells, 181,259 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 10 logic cells, 882 transistors 2,579 logic cells, 53,044 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors 0 logic cells, 0 transistors gf180mcu_fd_ip_sram__sram256x8m8wm1 Densest SRAM-free mm²: 12,266 logic cells 0 0 0 0 0 0 0 0 0 2k 0 0 <1k 12k 0 0 <1k 3k 0 0

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (12k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram256x8m8wm11 2,048

SERV multi-core RISC-V SoC has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Tiny Tapeout 2 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
  2. Dec 2022 · Google GFMPW-0 6079 Serv tri-core (GF180 MPW0 Serv) — Caravel chip, three SERV cores
  3. Apr 2023 · Tiny Tapeout 3 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
  4. Dec 2025 · wafer.space Run 1 GD02 Racquet Half r1p0 (1/2 slot) — ½ × 1 slot GD03 Racquet r2p0 - 23 core SoC — 1 × 1 slot, 23 SERV cores GD04 Racquet Wide 1x0.5 — 1 × ½ slot
  5. Jul 2026 · wafer.space Run 2 GD04 Racquet Wide 1x0.5 — 1 × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 6079 1 × 17t-5V 5 V/6 V only 17,345 2k 12k 1 macro
wafer.space Run 1 · GD02 ½ × 17t-5V 5 V/6 V only 34,564 8k 12k 9 macros
wafer.space Run 1 · GD03 1 × 17t-5V 5 V/6 V only 78,208 6k 0 23 macros
wafer.space Run 1 · GD04 1 × ½9t-5V 5 V/6 V only 35,525 7k 18k 6 macros
wafer.space Run 2 · GD04
the same logic cells and transistors as GD04 on wafer.space Run 1		 1 × ½9t-5V 5 V/6 V only 35,525 7k 18k 6 macros

From Tiny Tapeout tiles to a die of its own

SERV multi-core RISC-V SoC was tried on Tiny Tapeout 2, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

Reserve a slot
Start with Tiny Tapeout
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