Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Inside the core logic cells per mm² | 7k
(12% of buffer maximum) over the 5.02 mm² core: what the design itself packed |
|---|---|
| Inside the seal ring logic cells per mm² | 4k
over all 9.61 mm² of the slot, pad ring included |
| Densest mm² logic cells per mm² | 18k (31% of buffer maximum) |
| Core covered by logic | 28% |
| Transistor density transistors per mm² | 198k average, 234k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
A Configuration of racquet, a multicore Serv based SoC
- 9t 5v0 standard cells
- Difetto to incorporate DFT scan chain into design
- 6 cores
Source repository Die photographBonding results
| Die | 3.93 × 2.53 mm (9.9 mm²) |
|---|---|
| Core area | 5.02 mm² inside the pad ring
as set in the design's own layout settings |
| Inside the seal ring | 9.61 mm² (the die less its 26 µm seal ring) |
| Placements | 2 on the reticle, in slots D1, F1 |
| Bond pads | 72 |
| Transistors | 992,924 |
| Logic cells | 35,525 + 104,165 filler and tap cells |
| Libraries | 9t-5V (36k) |
| SRAM | 6 macros, 24,576 bits |
Submission
| Licence | BSD-3-Clause declared
Repository: Apache-2.0 in LICENSE, not the declared licence |
|---|---|
| Template | wafer-space/gf180mcu-project-template 1.3.1 or 1.3.2 |
| How it was checked | Commit and PDK pinThe licence and template were read from the repository at commit a64a899dabd2.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4). |
| Chip-on-board | Not selected at submission · bonding results |
| Precheck | Passed
the check it was accepted on, 2025-12-17, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-07-30, gf180mcu-precheck 1.7.3 step results and logs |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 9t-5V standard cells, fd SRAM |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
| I/O library | gf180mcu_fd_io (742 cells), gf180mcu_ws_io (16 cells) |
Where the area went
How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.
- Logic cells 1.40 mm² (14%)
- SRAM 1.26 mm² (13%)
- Filler and tap cells 2.26 mm² (23%)
- Other 0.10 mm² (1%)
- Pad ring 4.92 mm² (50%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| nand2_1 | 9t-5V | 7,375 | 2-input NAND gate |
| dlyd_1 | 9t-5V | 2,774 | Delay buffer |
| oai21_1 | 9t-5V | 2,556 | OR-AND-Invert compound gate |
| clkinv_1 | 9t-5V | 2,456 | Clock inverter |
| sdffrnq_1 | 9t-5V | 1,993 | Scan D flip-flop with reset |
| sdffq_1 | 9t-5V | 1,434 | Scan D flip-flop |
| oai21_2 | 9t-5V | 1,369 | OR-AND-Invert compound gate (2x drive) |
| nand3_1 | 9t-5V | 1,346 | 3-input NAND gate |
| clkbuf_8 | 9t-5V | 1,129 | Clock buffer (8x drive) |
| nand2_2 | 9t-5V | 1,105 | 2-input NAND gate (2x drive) |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (18k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.
SRAM macros
The ready-made memory blocks this design uses.
| Macro | Count | Bits each |
|---|---|---|
| gf180mcu_fd_ip_sram__sram512x8m8wm1 | 6 | 4,096 |
How this design grew
SERV multi-core RISC-V SoC has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:
- Dec 2022 · Tiny Tapeout 2 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
- Dec 2022 · Google GFMPW-0 6079 Serv tri-core (GF180 MPW0 Serv) — Caravel chip, three SERV cores
- Apr 2023 · Tiny Tapeout 3 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
- Dec 2025 · wafer.space Run 1 GD04 Racquet Wide 1x0.5 — 1 × ½ slot GD02 Racquet Half r1p0 (1/2 slot) — ½ × 1 slot GD03 Racquet r2p0 - 23 core SoC — 1 × 1 slot, 23 SERV cores
- Jul 2026 · wafer.space Run 2 GD04 Racquet Wide 1x0.5 — 1 × ½ slot
Tiny Tapeout tile Google shuttle wafer.space die
Its dies compared
Every die of this design measured here, oldest first, with this one in bold.
| Made on | Slot | Library | Gate oxides | Logic cells | Per mm² of core | Densest | SRAM |
|---|---|---|---|---|---|---|---|
| Google GFMPW-0 · 6079 | 1 × 1 | 7t-5V | 5 V/6 V only | 17,345 | 2k | 12k | 1 macro |
| wafer.space Run 1 · GD02 | ½ × 1 | 7t-5V | 5 V/6 V only | 34,564 | 8k | 12k | 9 macros |
| wafer.space Run 1 · GD03 | 1 × 1 | 7t-5V | 5 V/6 V only | 78,208 | 6k | 0 | 23 macros |
| wafer.space Run 1 · GD04 | 1 × ½ | 9t-5V | 5 V/6 V only | 35,525 | 7k | 18k | 6 macros |
| wafer.space Run 2 · GD04 the same logic cells and transistors as GD04 on wafer.space Run 1 |
1 × ½ | 9t-5V | 5 V/6 V only | 35,525 | 7k | 18k | 6 macros |
From Tiny Tapeout tiles to a die of its own
SERV multi-core RISC-V SoC was tried on Tiny Tapeout 2 and a Google shuttle, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.
The fabricated die
A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0
Precheck
Before a design is made, the wafer.space platform checks it against the foundry's design rules. GD04 was accepted on this check, and has been checked again since with newer rules.
All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-17.
Every step, and the latest re-run
| Step | Accepted on check 155, 2025-12-17, drc_update, gf180mcu-precheck 1.5.5 (from its image) PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e | Latest re-run check 701, 2026-07-30, drc_update, gf180mcu-precheck 1.7.3 PDK open_pdks 1.0.604, LibreLane 5fe3db1 |
|---|---|---|
| KLayout.ReadLayout | passed | passed |
| KLayout.CheckTopLevel | passed | passed |
| KLayout.CheckSize | passed | passed |
| KLayout.GenerateID | passed | passed |
| KLayout.Render | not in this flow | passed |
| KLayout.Density | passed | passed |
| Checker.KLayoutDensity | passed | passed |
| KLayout.ZeroAreaPolygons | passed | passed |
| Checker.KLayoutZeroAreaPolygons | passed | passed |
| KLayout.Antenna | passed | passed |
| Checker.KLayoutAntenna | passed | passed |
| Magic.DRC | passed | passed |
| Checker.MagicDRC | advisory warning | advisory warning |
| KLayout.DRC | passed | passed |
| Checker.KLayoutDRC | passed | passed |
| KLayout.WriteLayout | passed | passed |
| KLayout DRC errors | 0 | 0 |
| Magic DRC errors (advisory) | 3,122 | 3,122 |
| Files | steps · log (gzip) | steps · log (gzip) |
The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.