wafer.space Run 1

Racquet r2p0 - 23 core SoC

GD03 · RISC-V and CPUs · 1 × 1 slot

Layout render of Racquet r2p0 - 23 core SoC

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²		6k (8% of buffer maximum)
over the 12.92 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²		4k
over all 19.65 mm² of the slot, pad ring included
Core covered by logic17%
Transistor density
transistors per mm²		211k average

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

An SoC based off the award-winning SERV, the world’s smallest RISC-V CPU. With all the room available in the full-slot we can fit 23 cores connected to local SRAM. Each core is loaded from SPI FLASH on boot, and connected to a slew of peripherals: uarts, timers and more uarts. A queue peripheral enables both synchronisation and core-core communications.

Source repository Die photograph

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.92 mm² inside the pad ring
as set in the design's own layout settings
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot D2 GD03 on the reticle
Bond pads74
Transistors2,730,062
Logic cells78,208 + 241,732 filler and tap cells
Libraries 7t-5V (78k)
SRAM23 macros, 94,208 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
Templatewafer-space/gf180mcu-project-template 1.3.1 or 1.3.2
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 5ef4901d472d.The template releases named above are the ones whose Makefile pins the same PDK as that commit (PDK_TAG 1.6.4).
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2025-12-17, gf180mcu-precheck 1.5.5 (from its image)
Passed latest re-run, 2026-07-09, gf180mcu-precheck 1.7.1 (from its image)
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells, fd SRAM
Gate oxidesThick only (5 V/6 V) in the design itself
I/O librarygf180mcu_fd_io (1122 cells), gf180mcu_ws_io (18 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

11%
24%
27%
36%
  • Logic cells 2.17 mm² (11%)
  • SRAM 4.82 mm² (24%)
  • Filler and tap cells 5.44 mm² (27%)
  • Other 0.49 mm² (2%)
  • Pad ring 7.20 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 9,5752-input NAND gate
dffq_17t-5V 5,201D flip-flop (1 bit storage)
aoi21_17t-5V 4,951AND-OR-Invert compound gate
oai21_17t-5V 4,909OR-AND-Invert compound gate
nor2_17t-5V 4,8222-input NOR gate
buf_47t-5V 3,797Buffer (4x drive)
dlyb_17t-5V 3,712Delay buffer
clkinv_17t-5V 3,624Clock inverter
dlyc_17t-5V 3,343Delay buffer
oai211_17t-5V 3,288OR-AND-Invert compound gate

Logic density map

56 logic cells, 54,254 transistors, 21% SRAM 2,342 logic cells, 129,330 transistors, 15% SRAM 1,588 logic cells, 112,806 transistors, 12% SRAM 43 logic cells, 47,335 transistors, 22% SRAM 1,136 logic cells, 111,274 transistors, 21% SRAM 10,497 logic cells, 230,064 transistors, 36% SRAM 9,010 logic cells, 217,293 transistors, 33% SRAM 352 logic cells, 96,298 transistors, 22% SRAM 355 logic cells, 109,411 transistors, 21% SRAM 10,170 logic cells, 220,607 transistors, 36% SRAM 11,515 logic cells, 220,822 transistors, 33% SRAM 1,320 logic cells, 99,141 transistors, 22% SRAM 901 logic cells, 111,122 transistors, 21% SRAM 9,674 logic cells, 222,516 transistors, 36% SRAM 10,316 logic cells, 218,489 transistors, 33% SRAM 760 logic cells, 97,945 transistors, 22% SRAM 390 logic cells, 70,766 transistors, 21% SRAM 3,172 logic cells, 153,796 transistors, 20% SRAM 4,568 logic cells, 145,558 transistors, 18% SRAM 43 logic cells, 60,389 transistors, 22% SRAM 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 gf180mcu_fd_ip_sram__sram512x8m8wm1 <1k 2k 2k <1k 1k 10k 9k <1k <1k 10k 12k 1k 1k 10k 10k 1k <1k 3k 5k <1k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram512x8m8wm123 4,096

SERV multi-core RISC-V SoC has been made on 5 shuttles since Dec 2022. Every version, oldest first, with this one in bold:

  1. Dec 2022 · Tiny Tapeout 2 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
  2. Dec 2022 · Google GFMPW-0 6079 Serv tri-core (GF180 MPW0 Serv) — Caravel chip, three SERV cores
  3. Apr 2023 · Tiny Tapeout 3 serv - Serial RISC-V CPU — 1 × 1 tile, one SERV core
  4. Dec 2025 · wafer.space Run 1 GD03 Racquet r2p0 - 23 core SoC — 1 × 1 slot, 23 SERV cores GD02 Racquet Half r1p0 (1/2 slot) — ½ × 1 slot GD04 Racquet Wide 1x0.5 — 1 × ½ slot
  5. Jul 2026 · wafer.space Run 2 GD04 Racquet Wide 1x0.5 — 1 × ½ slot

Tiny Tapeout tile Google shuttle wafer.space die

Its dies compared

Every die of this design measured here, oldest first, with this one in bold.

Made onSlotLibraryGate oxides Logic cellsPer mm² of coreDensest SRAM
Google GFMPW-0 · 6079 1 × 17t-5V 5 V/6 V only 17,345 2k 12k 1 macro
wafer.space Run 1 · GD02 ½ × 17t-5V 5 V/6 V only 34,564 8k 12k 9 macros
wafer.space Run 1 · GD03 1 × 17t-5V 5 V/6 V only 78,208 6k 0 23 macros
wafer.space Run 1 · GD04 1 × ½9t-5V 5 V/6 V only 35,525 7k 18k 6 macros
wafer.space Run 2 · GD04
the same logic cells and transistors as GD04 on wafer.space Run 1		 1 × ½9t-5V 5 V/6 V only 35,525 7k 18k 6 macros

From Tiny Tapeout tiles to a die of its own

SERV multi-core RISC-V SoC was tried on Tiny Tapeout 2 and a Google shuttle, and went on to dies of its own on wafer.space Run 1 and wafer.space Run 2.

The fabricated die

A photograph of the finished chip, taken through a microscope after manufacture: optical micrograph © 2026 InfoSecDJ, CC BY-SA 4.0

Die photograph of Racquet r2p0 - 23 core SoC by InfoSecDJ

InfoSecDJ's zoomable viewer · Larger image · full resolution (very large file) · all photographs

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. GD03 was accepted on this check, and has been checked again since with newer rules.

All 15 steps passed, with 0 KLayout DRC errors, on 2025-12-17.

Every step, and the latest re-run
StepAccepted on
check 156, 2025-12-17, drc_update, gf180mcu-precheck 1.5.5 (from its image)
PDK wafer-space/gf180mcu 1.6.6, LibreLane e2f0b0e		Latest re-run
check 414, 2026-07-09, retry, gf180mcu-precheck 1.7.1 (from its image)
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Rendernot in this flowpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCpassedpassed
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)00
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.

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