Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless
PWM / Wishbone core
8BB5 · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
Logic density
| Core average logic cells per mm² | <1k (<1% of buffer maximum) |
|---|---|
| Densest mm² logic cells per mm² | 2k (3% of buffer maximum) |
| Core covered by logic | 1% |
| Transistor density transistors per mm² | 12k average, 108k in the mm² with the most logic cells |
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Eight synchronised 8-bit programmable PWMs controlled by a Wishbone slave interface.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle, in slot E8 |
| Bond pads | 63 |
| Transistors | 108,042 |
| Logic cells | 2,471 + 24,410 filler and tap cells |
| Libraries | 7t-5V (2k) |
| SRAM | No SRAM |
Process features
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
Where the area went
How this design's area splits between logic cells, filler and tap cells, other and outside the user area.
- Logic cells 0.06 mm² (<1%)
- Filler and tap cells 0.44 mm² (2%)
- Other 8.49 mm² (42%)
- Outside the user area 11.12 mm² (55%)
Most used cells
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 610 | Clock buffer |
| mux4_1 | 7t-5V | 231 | 4-input multiplexer |
| clkinv_1 | 7t-5V | 171 | Clock inverter |
| oai21_1 | 7t-5V | 146 | OR-AND-Invert compound gate |
| buf_1 | 7t-5V | 145 | Buffer |
| dffq_1 | 7t-5V | 145 | D flip-flop (1 bit storage) |
| nor2_1 | 7t-5V | 115 | 2-input NOR gate |
| aoi22_1 | 7t-5V | 109 | AND-OR-Invert (2x2 inputs) |
| nand2_1 | 7t-5V | 104 | 2-input NAND gate |
| and2_1 | 7t-5V | 80 | 2-input AND gate |
Logic density map
Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (2k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.