Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless
1F37 · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
154 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
Sequencer for a traffic light with a walk button, with timings tuned to match the iconic 'beep boop' streetlight formerly installed in front of Carnegie Mellon University. By Anish Singhani.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle, in slot C1 |
| Bond pads | 63 |
| Transistors | 82,002 |
| Logic cells | 154 + 11,448 filler and tap cells |
| Libraries | 7t-5V (154) |
| SRAM | No SRAM |
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
How this design's area splits between filler and tap cells, other and outside the user area.
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 26 | Clock buffer |
| dffq_1 | 7t-5V | 16 | D flip-flop (1 bit storage) |
| nor3_1 | 7t-5V | 10 | 3-input NOR gate |
| nand2_1 | 7t-5V | 9 | 2-input NAND gate |
| clkinv_1 | 7t-5V | 8 | Clock inverter |
| dlyb_1 | 7t-5V | 8 | Delay buffer |
| nor2_1 | 7t-5V | 8 | 2-input NOR gate |
| buf_1 | 7t-5V | 6 | Buffer |
| clkbuf_3 | 7t-5V | 6 | Clock buffer (3x drive) |
| nor4_1 | 7t-5V | 6 | 4-input NOR gate |