Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless
F330 · Other digital · 1 × 1 slot
Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings
388 logic cells: too few for density figures, which are given for designs of 1,000 or more.
Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.
A dual port register file plus an XNOR test gate. By Rolf Widenfelt.
| Die | 3.93 × 5.12 mm (20.1 mm²) |
|---|---|
| Core area | 9.00 mm² inside the pad ring
its user_project_wrapper cell |
| Placements | 1 on the reticle, in slot E7 |
| Bond pads | 63 |
| Transistors | 82,161 |
| Logic cells | 388 + 12,634 filler and tap cells |
| Libraries | 7t-5V (388) |
| SRAM | No SRAM |
Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.
| 5 V | 7t-5V standard cells |
|---|---|
| Gate oxides | Thick only (5 V/6 V) in the design itself |
How this design's area splits between logic cells, filler and tap cells, other and outside the user area.
The ten standard cells this design uses most.
| Cell | Library | Instances | What it does |
|---|---|---|---|
| clkbuf_1 | 7t-5V | 96 | Clock buffer |
| dffq_1 | 7t-5V | 64 | D flip-flop (1 bit storage) |
| mux2_2 | 7t-5V | 64 | 2-input multiplexer (2x drive) |
| mux4_1 | 7t-5V | 32 | 4-input multiplexer |
| dlyb_1 | 7t-5V | 28 | Delay buffer |
| clkbuf_2 | 7t-5V | 14 | Clock buffer (2x drive) |
| buf_1 | 7t-5V | 10 | Buffer |
| nand2_1 | 7t-5V | 10 | 2-input NAND gate |
| clkbuf_3 | 7t-5V | 9 | Clock buffer (3x drive) |
| aoi21_1 | 7t-5V | 8 | AND-OR-Invert compound gate |