Google GF180MCU open shuttle (GFMPW‑0) · Run by Google and Efabless

16 x 4-bit dual port register file

F330 · Other digital · 1 × 1 slot

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

388 logic cells: too few for density figures, which are given for designs of 1,000 or more.

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

A dual port register file plus an XNOR test gate. By Rolf Widenfelt.

Die3.93 × 5.12 mm (20.1 mm²)
Core area9.00 mm² inside the pad ring
its user_project_wrapper cell
Placements1 on the reticle, in slot E7 F330 on the reticle
Bond pads63
Transistors82,161
Logic cells388 + 12,634 filler and tap cells
Libraries 7t-5V (388)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this design's area splits between logic cells, filler and tap cells, other and outside the user area.

43%
55%
  • Logic cells 0.01 mm² (<1%)
  • Filler and tap cells 0.37 mm² (2%)
  • Other 8.62 mm² (43%)
  • Outside the user area 11.12 mm² (55%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
clkbuf_17t-5V 96Clock buffer
dffq_17t-5V 64D flip-flop (1 bit storage)
mux2_27t-5V 642-input multiplexer (2x drive)
mux4_17t-5V 324-input multiplexer
dlyb_17t-5V 28Delay buffer
clkbuf_27t-5V 14Clock buffer (2x drive)
buf_17t-5V 10Buffer
nand2_17t-5V 102-input NAND gate
clkbuf_37t-5V 9Clock buffer (3x drive)
aoi21_17t-5V 8AND-OR-Invert compound gate

Want a chip of your own like this one?

wafer.space Run 3 takes orders until 9 December 2026. Or start smaller with Tiny Tapeout: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3.