Tiny Tapeout GF 0.3 · Die T0P3 on wafer.space Run 2

MCML VCO

454 · Analog and mixed-signal · 1 × 2 tiles

by Namibj

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

An MCML VCO

Size347 × 325 µm (0.113 mm²)
Macrott_um_mcml_vco
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 0.3
Tiles1 × 2 at column 7, row 3 of the tile grid
Mux address454
LanguageAnalog
Transistors52
Logic cells0
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V52 custom transistors
Gate oxidesThin only (3.3 V) in the design itself
High-resistance poly resistors16 (352 µm²)

Where the area went

All of this project's area is other.

100%
  • Other 0.12 mm² (100%)

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.