What was built

The chip as a whole: what its projects add up to.

95

Projects

on the chip

89

Open source

with a public repository

2.4M

Transistors

across the unique designs

138k

Logic cells

gates and flip-flops

256 bytes

SRAM

in foundry and custom macros

Counted inside the projects only, so these totals are smaller than the die's own figures on its run's page: the pads, Tiny Tapeout's multiplexer and controller and the fill are left out.

Get this chip, or make your own

Tiny Tapeout puts many small designs on one chip. Start with a tile, then come back with a whole die.

1
Get a Tiny Tapeout chip

Every Tiny Tapeout chip comes on a board you can plug in, with all of its projects ready to try.

Buy a chip and board
2
Put your design on the next one

Tiny Tapeout GF 26c and 26d take projects until 7 December 2026, to be made on wafer.space Run 3.

Submit a project
3
Make a whole chip of your own

When a design outgrows a few tiles, it can have a die to itself on wafer.space Run 3: orders close 9 December 2026.

Reserve a slot

The die

Every design rendered from the layout at the same scale and placed where it sits on the 3.9 × 5.1 mm die. Point at a project to see its name, and select it for its details.Every project is listed further down.

Project sizes

How many tiles each project took. A tile is the smallest piece of a Tiny Tapeout chip you can submit a design to.

1 × 1 tiles72
1 × 2 tiles17
2 × 2 tiles2
3 × 2 tiles1
4 × 2 tiles1
4 × 4 tiles2
Total95

Layout on GitHub

Shuttle status

Two schedules meet here: Tiny Tapeout collects the projects and builds the die, then wafer.space manufactures it on wafer.space Run 2 and ships the parts.

Done so far

  • wafer.space 1 March 2026 Campaign opens Run 2 slots available for purchase on Crowd Supply
  • wafer.space 30 April 2026, 23:59 AoE Early bird deadline Last day to purchase at early bird pricing, for whole-die slots on the run (not Tiny Tapeout projects)
  • Tiny Tapeout 22 June 2026 Tiny Tapeout GF 26a submissions close Last day to submit a project to this Tiny Tapeout shuttle
  • wafer.space 30 June 2026, 23:59 AoE Purchase deadline Final deadline to purchase slots, for whole-die slots on the run (not Tiny Tapeout projects)
  • Tiny Tapeout 4 July 2026 Tiny Tapeout GF 26a tapeout release Tiny Tapeout publishes the die's layout (tapeout-ws2607) and sends it to wafer.space
  • wafer.space 14 July 2026, 23:59 AoE Submission deadline Final deadline to submit clean GDS
  • wafer.space 22 July 2026 Tape-out to GlobalFoundries GDS files delivered to GlobalFoundries for fabrication
  • wafer.space 30 July 2026 Masks released Masks approved and fabrication started
  • wafer.space 17 September 2026 First wafers returned An initial set of wafers back from GlobalFoundries
  • wafer.space 8 October 2026 First wafers diced The initial wafers cut into individual dies

Still to come

  • Today, 24 October 2026
  • wafer.space 22 October 2026 (expected) First dies sorted Dies from the initial wafers picked and sorted by project
  • wafer.space 22 October 2026 (expected) First bare dies shipped Initial bare dies shipped to customers
  • wafer.space 12 November 2026 (expected) First packaged parts shipped Initial chip-on-board packaged parts shipped
  • wafer.space 10 December 2026 (expected) Main wafer lot returned The first full lot of Run 2 wafers back from GlobalFoundries
  • wafer.space 31 December 2026 (expected) Main lot bare dies shipped Bare dies from the main lot shipped to customers
  • wafer.space 15 January 2027 (expected) Last wafer lot returned The rest of the Run 2 wafers back from GlobalFoundries
  • wafer.space 21 January 2027 (expected) Main lot packaged parts shipped Chip-on-board packaged parts from the main lot shipped
  • wafer.space 5 February 2027 (expected) Last lot bare dies shipped Bare dies from the last lot shipped to customers
  • wafer.space 26 February 2027 (expected) Last lot packaged parts shipped Chip-on-board packaged parts from the last lot shipped

Missed this one? Tiny Tapeout GF 26c and 26d take projects until 7 December 2026: submit a project.

From the wafer.space run schedule and the Tiny Tapeout GF 26a repository.

How people used their silicon

Where the area of 95 projects (9 mm² of silicon) actually went

42%
49%
  • Logic cells 42% — gates and flip-flops doing the design's actual work
  • SRAM 2% — memory macros
  • Filler and tap cells 49% — inserted by the tools to keep rows continuous and wells tied
  • Other 6% — routing channels, analog and custom layout, power grid and empty space

Standard cell libraries

The ready-made gate libraries the designs were built from: how many tracks tall each cell is, and the voltage it runs at.

Standard cell libraryLogic cellsShare
7t-5V gf180mcu_fd_sc_mcu7t5v0 138k 100%
9t-5V gf180mcu_fd_sc_mcu9t5v0 48 <1%

Area budget of every design

Each bar is one project, split the same way as above. Sorted by how much of the project is logic.

Show all 95 projects
551 Tiny Quantum Circuit Simulator 578 Balanced Ternary Multiplier 549 Ring Oscillator PVT Sensor & TRNG (GF180) 454 Tensor Processing Unit For GF 547 Memristive Crossbar Peripheral Controller (GF180) 129 7-Segment Neural Predictor 358 Stochastic neuron + STDP controller (merged, GF180) 450 Simple MAC Engine w/ Postproc 039 Programmable_Pipeline-RISC-V 611 UNIZG-FER VGA project 034 2x2 MAC Systolic array with DFT 355 Simon Says memory game 195 Tiny Pixel Processor 581 SPI-Controlled 8-Channel LED Driver 384 teenytpu 577 Custom DVD Screensaver for VGA 096 wafer.space Logo VGA Screensaver 032 Hardware UTF Encoder/Decoder 519 Number Memory Game 513 rgb_mixer 102 Custom DVD Screensaver for VGA 070 xoroshiro64 452 Simple Signal Generator 100 Dino-7: 7-Segment Runner Game 069 MIPS-Lite 8-bit Processor 007 2x2 Systolic Array Matrix Multiplier 517 Ball Display 354 8-bit RISC CPU 448 APA102 to WS2812 Translator 295 UTOSS RISC-V core 579 VGA_screensaver_UACJ 388 Tiny TPU Systolic Array 199 Very Low Resource Digital Implementation of Bioimpedance Analysis 613 Dyadic PWM 480 spiPWMio 583 Universal Binary to Segment Decoder 098 happyhop 576 Tiny Number Simon 386 Pong in Verilog 103 Minimal RV32E SoC with UART Loader 484 BIST-8: Built-In Self-Test for 8-bit CLA Adder 068 Line Follower Robot controller 192 Gen1 Digital Companion Tile 515 microlane demo project 000 Chip ROM 518 ocxpkeWokwiDesign 001 Tiny Tapeout Factory Test 003 Counter16Outputs 609 VCO driven by DAC 512 Tiny Tapeout JMCG 487 Tiny Tapeout RJAP 194 Tiny Tapeout Template Ayman 580 Tiny Tapeout Workshop Malaga 2jun2026 614 ram 1 bit Copy 066 sdft wokwi 1 389 Arturo's first Wokwi design 359 Tiny Tapeout testtest 111233 455 Matt’s first Wokwi design 387 Tiny Tapeout Template_1234 198 Tiny Tapeout Template Copy 065 Antonio's first Wokwi design 196 Julian_Proyecto 128 Tiny Tapeout Template Copy 612 Tiny Tapeout Template 451 7 segment Display Fli-Flop Try-out 514 Paula's first Wokwi design 481 Basic Circuit 483 El primer diseño de Matt para Wokwi 485 Tiny Tapeout Template flip flop 130 El primer diseño 449 Rafa’s first Wokwi design 134 test1 067 Guille's first Wokwi design. 582 Simple Sprinkler 132 Mi copia del Tiny Tapeout 610 Tiny Tapeout Marcos Fernandez 071 Juan`s first Worki design 357 First Tinytapeout 385 Tiny Tapeout Workshop JuanF 391 Pacos first design 516 Pedro Template 608 Rhyloo’s first Wokwi design 453 DiseñoCursoTiny

Which parts of the process were used

Transistor voltages and optional devices across the 95 designs

Transistor voltages

3.3 V 1
5 V 95

A design counts for a voltage when its standard cells, SRAM or its own transistors use it. 5 V and 6 V transistors share the thick gate oxide; a marker layer in the layout tells them apart.

Optional devices drawn by designers

DeviceDesignsWhich
High-resistance poly resistors1 VCO driven by DAC

Not drawn by any design: Native transistors, 10 V LDMOS, MIM capacitors, MOS capacitors, Unsalicided poly resistors, Salicided poly resistors, Diffusion resistors, N-well resistors, Metal resistors, Diodes, Well diodes, Deep N-well, Bipolar transistors, Schottky diodes, Zener diodes, eFuses, One-time programmable memory, Inductors.

Only devices outside standard cells, SRAM macros and I/O pads count, since every die has those. A single test structure counts the same as a large block.

Gate oxides

TransistorsDesignsWhich
3.3 V and 5 V/6 V 1 VCO driven by DAC
3.3 V only 0
5 V/6 V only 94
94 projectsChip ROM, Tiny Tapeout Factory Test, Counter16Outputs, 2x2 CNN Accelerator PE Grid with UART, 2x2 Systolic Array Matrix Multiplier, Hardware UTF Encoder/Decoder, 2x2 MAC Systolic array with DFT, FSK Modem, RRAM Characterization Platform (DC sweep + endurance + retention + histogram, GF180), Programmable_Pipeline-RISC-V, Antonio's first Wokwi design, sdft wokwi 1, Guille's first Wokwi design., Line Follower Robot controller, MIPS-Lite 8-bit Processor, xoroshiro64, Juan`s first Worki design, wafer.space Logo VGA Screensaver, happyhop, Dino-7: 7-Segment Runner Game, Custom DVD Screensaver for VGA, Minimal RV32E SoC with UART Loader, Tiny Tapeout Template Copy, 7-Segment Neural Predictor, El primer diseño, Mi copia del Tiny Tapeout, test1, serv_soc_wb, Gen1 Digital Companion Tile, Tiny Tapeout Template Ayman, Tiny Pixel Processor, Julian_Proyecto, Tiny Tapeout Template Copy, Very Low Resource Digital Implementation of Bioimpedance Analysis, UTOSS RISC-V core, Hardware Entropy Explorer: UART/SPI TRNG and PUF, DOTTEE VGA demo (TTGF26a), 8-bit RISC CPU, Simon Says memory game, RHD2164-MCU-SPI Bridge, First Tinytapeout, Stochastic neuron + STDP controller (merged, GF180), Tiny Tapeout testtest 111233, teenytpu, Tiny Tapeout Workshop JuanF, Pong in Verilog, Tiny Tapeout Template_1234, Tiny TPU Systolic Array, Arturo's first Wokwi design, GPS_Accelerator, Pacos first design, APA102 to WS2812 Translator, Rafa’s first Wokwi design, Simple MAC Engine w/ Postproc, 7 segment Display Fli-Flop Try-out, Simple Signal Generator, DiseñoCursoTiny, Tensor Processing Unit For GF, Matt’s first Wokwi design, spiPWMio, Basic Circuit, SAP 8 Bit Computer, El primer diseño de Matt para Wokwi, BIST-8: Built-In Self-Test for 8-bit CLA Adder, Tiny Tapeout Template flip flop, BioPulse Tile, Tiny Tapeout RJAP, Tiny Tapeout JMCG, rgb_mixer, Paula's first Wokwi design, microlane demo project, Pedro Template, Ball Display, ocxpkeWokwiDesign, Number Memory Game, BF, Memristive Crossbar Peripheral Controller (GF180), Ring Oscillator PVT Sensor & TRNG (GF180), Tiny Quantum Circuit Simulator, Tiny Number Simon, Custom DVD Screensaver for VGA, Balanced Ternary Multiplier, VGA_screensaver_UACJ, Tiny Tapeout Workshop Malaga 2jun2026, SPI-Controlled 8-Channel LED Driver, Simple Sprinkler, Universal Binary to Segment Decoder, Rhyloo’s first Wokwi design, Tiny Tapeout Marcos Fernandez, UNIZG-FER VGA project, Tiny Tapeout Template, Dyadic PWM, ram 1 bit Copy, Video mode tester

3.3 V transistors have the thin gate oxide; 5 V and 6 V ones share the thick one.

What fits on 1 mm² of GF180MCU silicon?

Theoretical maximum against what designers achieved

The maximum packs one cell type edge to edge with no room for wiring. Real designs need the wiring. Each box gives the most of a cell that fits with any GF180MCU library, then with the libraries this chip used.

~114k

Inverters per mm²

GF180MCU maximum,
with AS 7t-3.3V inv_2

With this chip's libraries:

7t-5V: 114k inv_1

9t-5V: 89k inv_1

~91k

NAND gates per mm²

GF180MCU maximum,
with 7t-5V nand2_1

With this chip's libraries:

7t-5V: 91k nand2_1

9t-5V: 71k nand2_1

~76k

Buffers per mm²

GF180MCU maximum,
with AS 7t-3.3V buff_2

With this chip's libraries:

7t-5V: 76k buf_1

9t-5V: 59k buf_1

~17k

Flip-flops per mm²

GF180MCU maximum,
with AS 7t-3.3V dfxtp_2

With this chip's libraries:

7t-5V: 16k dffq_1

9t-5V: 13k dffq_1

34k

Best core average

logic cells/mm² of core — 45% of the buffer maximum

DOTTEE VGA demo (TTGF26a)

42k

Densest 0.1 mm square

logic cells per mm² — 55% of the buffer maximum

BioPulse Tile

23k

Typical project

median logic cells/mm² of core across 39 digital projects (1,000 or more logic cells)

65% of the core covered by logic cells

Percentages compare with the buffer maximum for each design's own library: buffers are among the smallest and most common logic cells, so a design made only of buffers, packed edge to edge with no wiring, would reach 100%.

Sizing your own design

What each tile size held on this chip, and what it would hold at its densities

Logic cells in its digital projects1,000 or more logic cells Logic cells at this chip's density Theoretical maximum, 7t-5V cells
Tiles Size  Core area Projects  Most Median  Typical23k / mm²Best34k / mm² NAND gatesnand2_1Flip-flopsdffq_1
1 × 10.35 × 0.16 mm 0.06 mm²72 1.9k1.3k 1.3k 1.9k 5.1k 880
1 × 20.35 × 0.33 mm 0.12 mm²17 3.5k2.6k 2.6k 4.0k 10.5k 1.8k
2 × 20.71 × 0.33 mm 0.23 mm²2 4.9k3.9k 5.3k 8.0k 21.3k 3.7k
3 × 21.08 × 0.33 mm 0.36 mm²1 10.0k10.0k 8.1k 12.2k 32.5k 5.6k
4 × 21.44 × 0.33 mm 0.48 mm²1 4.5k4.5k 10.7k 16.3k 43.3k 7.5k
4 × 41.44 × 0.74 mm 1.07 mm²2 23.2k19.2k 24.1k 36.5k 97.1k 16.7k

Swipe the table sideways for more columns.

Core area is the whole project. "Typical" and "best" multiply the core area by this chip's median and best core densities; SRAM and analog blocks take their area out of that. The theoretical maxima fill the core with nothing but that one cell of 7t-5V, the library most used on this chip, edge to edge with no routing.

Pick the tile size your design needs when you submit it to the next Tiny Tapeout chip, by 7 December 2026.

Logic density of every digital design

A digital project here is one with 1,000 or more logic cells. Solid bar: average over the core. Outlined bar: the densest 0.1 mm square outside SRAM, per mm² (a dash where memory covers most of the design). The scale ends at the buffer theoretical maximum (76k cells/mm²). The numbers are core / densest, in logic cells per mm².

Show all 39 digital projects
Every digital project's densities as a table
ProjectTilesLibraryLogic cells Inside core
per mm²
Densest 0.1 mm square
per mm²
Core coveredCore
mm²
DOTTEE VGA demo (TTGF26a) 353 1 × 17t-5V 1,919 34,268 40,000 81% 0.06*
BioPulse Tile 486 1 × 17t-5V 1,822 32,536 41,800 85% 0.06*
GPS_Accelerator 390 1 × 27t-5V 3,457 29,931 37,200 81% 0.12*
7-Segment Neural Predictor 129 1 × 27t-5V 3,389 29,342 34,300 69% 0.12*
Tiny Quantum Circuit Simulator 551 1 × 17t-5V 1,600 28,571 34,200 73% 0.06*
Hardware Entropy Explorer: UART/SPI TRNG and PUF 352 1 × 27t-5V 3,272 28,329 40,000 79% 0.12*
FSK Modem 036 1 × 27t-5V 3,243 28,078 36,000 77% 0.12*
serv_soc_wb 135 3 × 27t-5V 9,987 28,022 36,000 81% 0.36*
2x2 CNN Accelerator PE Grid with UART 005 1 × 17t-5V 1,536 27,429 35,900 80% 0.06*
BF 545 1 × 17t-5V 1,521 27,161 34,800 77% 0.06*
Balanced Ternary Multiplier 578 1 × 17t-5V 1,452 25,929 30,700 71% 0.06*
Tensor Processing Unit For GF 454 1 × 27t-5V 2,941 25,463 30,200 70% 0.12*
RRAM Characterization Platform (DC sweep + endurance + retention + histogram, GF180) 038 1 × 27t-5V 2,807 24,303 32,600 76% 0.12*
RHD2164-MCU-SPI Bridge 356 1 × 27t-5V 2,793 24,182 31,800 83% 0.12*
UNIZG-FER VGA project 611 1 × 17t-5V 1,334 23,821 29,000 65% 0.06*
teenytpu 384 1 × 27t-5V 2,687 23,264 37,000 61% 0.12*
Simon Says memory game 355 1 × 17t-5V 1,301 23,232 37,200 64% 0.06*
Video mode tester 615 1 × 17t-5V 1,287 22,982 27,700 75% 0.06*
Ring Oscillator PVT Sensor & TRNG (GF180) 549 1 × 17t-5V 1,266 22,607 28,500 70% 0.06*
2x2 MAC Systolic array with DFT 034 1 × 27t-5V 2,611 22,606 32,400 65% 0.12*
Simple MAC Engine w/ Postproc 450 1 × 27t-5V 2,601 22,519 28,500 65% 0.12*
Memristive Crossbar Peripheral Controller (GF180) 547 1 × 17t-5V 1,228 21,929 26,500 70% 0.06*
Hardware UTF Encoder/Decoder 032 1 × 17t-5V 1,220 21,786 36,100 51% 0.06*
Programmable_Pipeline-RISC-V 039 4 × 47t-5V 23,196 21,768 34,300 65% 1.07*
SAP 8 Bit Computer 482 1 × 17t-5V 1,214 21,679 27,600 77% 0.06*
Custom DVD Screensaver for VGA 577 1 × 17t-5V 1,204 21,500 29,000 54% 0.06*
Stochastic neuron + STDP controller (merged, GF180) 358 1 × 27t-5V 2,435 21,082 27,000 69% 0.12*
xoroshiro64 070 1 × 17t-5V 1,174 20,964 35,000 48% 0.06*
Tiny Pixel Processor 195 2 × 27t-5V 4,885 20,849 31,000 64% 0.23*
wafer.space Logo VGA Screensaver 096 1 × 27t-5V 2,228 19,290 27,300 53% 0.12*
Custom DVD Screensaver for VGA 102 1 × 17t-5V 1,039 18,554 28,100 48% 0.06*
APA102 to WS2812 Translator 448 1 × 27t-5V 1,899 16,442 33,300 42% 0.12*
8-bit RISC CPU 354 1 × 27t-5V 1,728 14,961 33,100 43% 0.12*
Simple Signal Generator 452 1 × 27t-5V 1,704 14,753 26,900 47% 0.12*
UTOSS RISC-V core 295 4 × 47t-5V 15,124 14,193 34,700 42% 1.07*
Tiny TPU Systolic Array 388 1 × 27t-5V 1,529 13,238 28,300 41% 0.12*
Very Low Resource Digital Implementation of Bioimpedance Analysis 199 2 × 27t-5V 2,825 12,057 23,100 39% 0.23*
Pong in Verilog 386 1 × 27t-5V 1,136 9,835 27,800 26% 0.12*
Minimal RV32E SoC with UART Loader 103 4 × 27t-5V 4,459 9,383 34,100 24% 0.48*

The projects

Every project on this chip: an index, then grouped by what it does. Select one for its layout, its measurements and any die photographs.

Project index

All 95 projects by their address on the chip's multiplexer, with how many tiles each took and how much logic it packs.

AddressProjectAuthorTiles What it isLogic cells Cells per mm²
000 Chip ROM Uri Shaked 1 × 1 Other digital 233 4k
001 Tiny Tapeout Factory Test Tiny Tapeout 1 × 1 Test structures 108 2k
003 Counter16Outputs Alvaro Rubio 1 × 1 Other digital 71 1k
005 2x2 CNN Accelerator PE Grid with UART Vidhyanandhan Sathishkumar 1 × 1 Accelerators 1,536 27k
007 2x2 Systolic Array Matrix Multiplier Irene-ux 1 × 1 Other digital 951 17k
032 Hardware UTF Encoder/Decoder Rebecca G. Bettencourt 1 × 1 Other digital 1,220 22k
034 2x2 MAC Systolic array with DFT Vijay Sharma 1 × 2 Other digital 2,611 23k
036 FSK Modem Vaishnavi V 1 × 2 Communications 3,243 28k
038 RRAM Characterization Platform (DC sweep + endurance + retention + histogram, GF180) Prof. Santhosh Sivasubramani, IIT Delhi 1 × 2 Test structures 2,807 24k
039 Programmable_Pipeline-RISC-V Prem 4 × 4 RISC-V and CPUs 23,196 22k
065 Antonio's first Wokwi design Antonio 1 × 1 First designs 16 <1k
066 sdft wokwi 1 Santiago Díaz Fernández de la Torre 1 × 1 Other digital 21 <1k
067 Guille's first Wokwi design. Guillermo 1 × 1 First designs 13 <1k
068 Line Follower Robot controller Escuela Colombiana de Ingenieria Julio Gravito 1 × 1 Other digital 302 5k
069 MIPS-Lite 8-bit Processor Jesus (jalperdev) 1 × 1 RISC-V and CPUs 880 16k
070 xoroshiro64 Vivek Chiranjit 1 × 1 Other digital 1,174 21k
071 Juan`s first Worki design Juan Andres 1 × 1 First designs 8 <1k
096 wafer.space Logo VGA Screensaver Uri Shaked 1 × 2 Art and logos 2,228 19k
098 happyhop deadcast2 1 × 1 Retro computing 580 10k
100 Dino-7: 7-Segment Runner Game Dr Sopes 1 × 1 Games 983 18k
102 Custom DVD Screensaver for VGA Jazmin Nayeli / Kensy Buatista 1 × 1 Retro computing 1,039 19k
103 Minimal RV32E SoC with UART Loader Kris / KLuterIRV 4 × 2 RISC-V and CPUs 4,459 9k
128 Tiny Tapeout Template Copy Pablo Ruiz 1 × 1 First designs 16 <1k
129 7-Segment Neural Predictor Abdul Hannan A. 1 × 2 Accelerators 3,389 29k
130 El primer diseño Maria Saldaña 1 × 1 First designs 13 <1k
132 Mi copia del Tiny Tapeout Antonio 1 × 1 First designs 12 <1k
134 test1 Alberto 1 × 1 First designs 13 <1k
135 serv_soc_wb Juan David Guerrero Balaguera 3 × 2 RISC-V and CPUs 9,987 28k
192 Gen1 Digital Companion Tile Juan Fernandez 1 × 1 Other digital 224 4k
194 Tiny Tapeout Template Ayman Ayman Harraz 1 × 1 First designs 27 <1k
195 Tiny Pixel Processor Julian Schlager, Thomas Lindinger, Patrick Pollak, Sebastian Gmeiner, Simon Vogelhuber 2 × 2 RISC-V and CPUs 4,885 21k
196 Julian_Proyecto Julián 1 × 1 Other digital 12 <1k
198 Tiny Tapeout Template Copy Alicia 1 × 1 First designs 18 <1k
199 Very Low Resource Digital Implementation of Bioimpedance Analysis Fabien 2 × 2 Other digital 2,825 12k
295 UTOSS RISC-V core University of Toronto Open Source Students 4 × 4 RISC-V and CPUs 15,124 14k
352 Hardware Entropy Explorer: UART/SPI TRNG and PUF gojimmypi 1 × 2 Security 3,272 28k
353 DOTTEE VGA demo (TTGF26a) algofoogle (Anton Maurovic) 1 × 1 Retro computing 1,919 34k
354 8-bit RISC CPU Jan Kozina 1 × 2 RISC-V and CPUs 1,728 15k
355 Simon Says memory game Uri Shaked 1 × 1 Games 1,301 23k
356 RHD2164-MCU-SPI Bridge Manuel Monge 1 × 2 Other digital 2,793 24k
357 First Tinytapeout Raúl 1 × 1 First designs 8 <1k
358 Stochastic neuron + STDP controller (merged, GF180) Prof. Santhosh Sivasubramani, IIT Delhi 1 × 2 Other digital 2,435 21k
359 Tiny Tapeout testtest 111233 Suresh Devanathan 1 × 1 First designs 21 <1k
384 teenytpu joannec34 1 × 2 Accelerators 2,687 23k
385 Tiny Tapeout Workshop JuanF Juan 1 × 1 First designs 8 <1k
386 Pong in Verilog Jorobraun, TnTim1, ColdC5 1 × 2 Games 1,136 10k
387 Tiny Tapeout Template_1234 Najlae 1 × 1 Other digital 16 <1k
388 Tiny TPU Systolic Array Yu Xia,Bohong Gao, Junjie Yan, Yufeng Wang, Jinyao Sun, Arthur Stanson 1 × 2 Accelerators 1,529 13k
389 Arturo's first Wokwi design Artcraft 1 × 1 First designs 20 <1k
390 GPS_Accelerator jpigdon 1 × 2 Accelerators 3,457 30k
391 Pacos first design Paco 1 × 1 First designs 8 <1k
448 APA102 to WS2812 Translator Squidgeefish 1 × 2 Other digital 1,899 16k
449 Rafa’s first Wokwi design Rafael Morales 1 × 1 First designs 12 <1k
450 Simple MAC Engine w/ Postproc Luca Goddijn 1 × 2 Other digital 2,601 23k
451 7 segment Display Fli-Flop Try-out Carlos David 1 × 1 Other digital 15 <1k
452 Simple Signal Generator Matt Venn 1 × 2 Other digital 1,704 15k
453 DiseñoCursoTiny José Ramñirez Díaz 1 × 1 First designs 4 <1k
454 Tensor Processing Unit For GF Mocus Zhang 1 × 2 Other digital 2,941 25k
455 Matt’s first Wokwi design Pedro Da Silva 1 × 1 First designs 20 <1k
480 spiPWMio Sönke Appel 1 × 1 Other digital 710 13k
481 Basic Circuit Izan Amador 1 × 1 Other digital 14 <1k
482 SAP 8 Bit Computer Navneet Prasad, Mohammed Riyaj J, Akash P, Vikash R 1 × 1 RISC-V and CPUs 1,214 22k
483 El primer diseño de Matt para Wokwi Marcos 1 × 1 First designs 14 <1k
484 BIST-8: Built-In Self-Test for 8-bit CLA Adder Mario Garcia Jimenez 1 × 1 Other digital 325 6k
485 Tiny Tapeout Template flip flop Nerea 1 × 1 First designs 12 <1k
486 BioPulse Tile Roberto Medina 1 × 1 Other digital 1,822 33k
487 Tiny Tapeout RJAP Rodrigo Álvarez 1 × 1 Other digital 28 1k
512 Tiny Tapeout JMCG Jose Manuel Cano Garcia 1 × 1 Other digital 38 1k
513 rgb_mixer divadnaujGB 1 × 1 Other digital 832 15k
514 Paula's first Wokwi design Paula García Jimémez 1 × 1 First designs 13 <1k
515 microlane demo project htfab 1 × 1 Other digital 365 7k
516 Pedro Template Pedro Barbero 1 × 1 First designs 8 <1k
517 Ball Display Daniel Penas 1 × 1 Retro computing 906 16k
518 ocxpkeWokwiDesign Jose Ramírez 1 × 1 First designs 168 3k
519 Number Memory Game Daniel Gabai & Shehroze Kiani 1 × 1 Games 787 14k
545 BF Joseph Wan and Joseph Mensah 1 × 1 Other digital 1,521 27k
547 Memristive Crossbar Peripheral Controller (GF180) Prof. Santhosh Sivasubramani, IIT Delhi 1 × 1 Analog and mixed-signal 1,228 22k
549 Ring Oscillator PVT Sensor & TRNG (GF180) Prof. Santhosh Sivasubramani, IIT Delhi 1 × 1 Test structures 1,266 23k
551 Tiny Quantum Circuit Simulator Oliver Hüttenhofer 1 × 1 Other digital 1,600 29k
576 Tiny Number Simon Ernesto M 1 × 1 Other digital 618 11k
577 Custom DVD Screensaver for VGA Alan Sigala 1 × 1 Retro computing 1,204 22k
578 Balanced Ternary Multiplier Serge Rabyking 1 × 1 Other digital 1,452 26k
579 VGA_screensaver_UACJ Angelica Morales Gallegos 1 × 1 Art and logos 868 16k
580 Tiny Tapeout Workshop Malaga 2jun2026 Martin Gonzalez Garcia 1 × 1 First designs 25 <1k
581 SPI-Controlled 8-Channel LED Driver Grace Eysenbach 1 × 1 Other digital 994 18k
582 Simple Sprinkler Noah Perez 1 × 1 Other digital 11 <1k
583 Universal Binary to Segment Decoder Rebecca G. Bettencourt 1 × 1 Other digital 606 11k
608 Rhyloo’s first Wokwi design Jorge Benavides Macías 1 × 1 First designs 7 <1k
609 VCO driven by DAC algofoogle (Anton Maurovic) 1 × 1 Analog and mixed-signal 48 1k
610 Tiny Tapeout Marcos Fernandez Marcos 1 × 1 First designs 10 <1k
611 UNIZG-FER VGA project Daniel Hofman 1 × 1 Retro computing 1,334 24k
612 Tiny Tapeout Template Sankori 1 × 1 First designs 16 <1k
613 Dyadic PWM Maksudjon Usmonov 1 × 1 Other digital 704 13k
614 ram 1 bit Copy siningua_alagartos 1 × 1 Other digital 22 <1k
615 Video mode tester htfab 1 × 1 Retro computing 1,287 23k

Swipe the table sideways for more columns.

Other digital 36

Show all 36 in Other digital

First designs 26

Show all 26 in First designs

RISC-V and CPUs 8

Retro computing 7

Accelerators 5

Games 4

Test structures 3

Art and logos 2

Analog and mixed-signal 2

Security 1

Communications 1

Die T26A on wafer.space Run 2

The die as a whole, measured like every other design on its run: its size, pads, process features, density, precheck and photographs. See every design on wafer.space Run 2

Rendered from the layout at 2.5 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Inside the core
logic cells per mm²
11k (15% of buffer maximum)
over the 12.90 mm² core: what the design itself packed
Inside the seal ring
logic cells per mm²
7k
over all 19.65 mm² of the slot, pad ring included
Densest mm²
logic cells per mm²
23k (30% of buffer maximum)
Core covered by logic33%
Transistor density
transistors per mm²
222k average, 297k in the mm² with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the run: see data and method, and how its designs used the process.

Die3.93 × 5.12 mm (20.1 mm²)
Core area12.90 mm² inside the pad ring
the project template's, 442 µm in from each edge
Inside the seal ring19.65 mm² (the die less its 26 µm seal ring)
Placements1 on the reticle, in slot A3 T26A on the reticle
Bond pads74
Transistors2,866,098
Logic cells144,419 + 318,284 filler and tap cells
Libraries 7t-5V (144k), 9t-5V (48)
SRAM2 macros, 2,048 bits

Submission

LicenceApache-2.0 declared
Repository: Apache-2.0 in LICENSE — agrees
How it was checked
Commit and PDK pin The licence and template were read from the repository at commit 35e70261e686.
Chip-on-boardNot selected at submission
PrecheckPassed the check it was accepted on, 2026-07-04
Passed latest re-run, 2026-08-02, gf180mcu-precheck 1.7.3
step results and logs

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

3.3 V24,850 custom transistors
5 V7t-5V standard cells, 9t-5V standard cells, fd SRAM
Gate oxidesThin (3.3 V) and thick (5 V/6 V) in the design itself
High-resistance poly resistors32 (190 µm²)
I/O librarygf180mcu_ocd_io (1140 cells)

Where the area went

How this design's area splits between logic cells, SRAM, filler and tap cells, other and pad ring.

21%
29%
12%
36%
  • Logic cells 4.25 mm² (21%)
  • SRAM 0.23 mm² (1%)
  • Filler and tap cells 5.90 mm² (29%)
  • Other 2.51 mm² (12%)
  • Pad ring 7.22 mm² (36%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 14,5642-input NAND gate
dffq_17t-5V 11,440D flip-flop (1 bit storage)
oai21_17t-5V 9,865OR-AND-Invert compound gate
nor2_17t-5V 7,6952-input NOR gate
dlyb_17t-5V 7,022Delay buffer
mux2_27t-5V 6,2892-input multiplexer (2x drive)
buf_27t-5V 5,930Buffer (2x drive)
aoi21_17t-5V 5,910AND-OR-Invert compound gate
clkinv_17t-5V 5,804Clock inverter
dffrnq_17t-5V 5,354D flip-flop with reset

Logic density map

1,402 logic cells, 62,883 transistors 2,136 logic cells, 97,508 transistors 5,298 logic cells, 117,423 transistors 901 logic cells, 53,648 transistors 9,120 logic cells, 135,773 transistors 14,013 logic cells, 215,942 transistors 11,942 logic cells, 227,842 transistors 5,947 logic cells, 112,236 transistors 8,344 logic cells, 141,576 transistors 11,331 logic cells, 223,983 transistors 8,056 logic cells, 215,113 transistors, 7% SRAM 2,788 logic cells, 94,437 transistors, 8% SRAM 9,017 logic cells, 152,296 transistors 17,695 logic cells, 264,650 transistors 14,777 logic cells, 221,250 transistors, 4% SRAM 5,262 logic cells, 100,449 transistors, 5% SRAM 4,573 logic cells, 90,045 transistors 7,683 logic cells, 149,039 transistors 2,625 logic cells, 121,886 transistors 1,509 logic cells, 67,273 transistors 0 logic cells, 176 transistors 0 logic cells, 256 transistors 0 logic cells, 255 transistors 0 logic cells, 159 transistors gf180mcu_fd_ip_sram__sram128x8m8wm1 gf180mcu_fd_ip_sram__sram128x8m8wm1 Densest SRAM-free mm²: 22,754 logic cells 1k 2k 5k 1k 9k 14k 12k 6k 8k 11k 8k 3k 9k 18k 15k 5k 5k 8k 3k 2k

Logic cells per mm² in each square millimetre of the die. Hatched outlines are SRAM macros; the red outline is the densest mm² that avoids them (23k logic cells per mm²), found by sliding a 1 mm square over the die in 0.1 mm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

SRAM macros

The ready-made memory blocks this design uses.

MacroCountBits each
gf180mcu_fd_ip_sram__sram128x8m8wm12 1,024

Precheck

Before a design is made, the wafer.space platform checks it against the foundry's design rules. T26A was accepted on this check, and has been checked again since with newer rules.

All 16 steps passed, with 0 KLayout DRC errors, on 2026-07-04.

Every step, and the latest re-run
StepAccepted on
check 334, 2026-07-04, initial
Latest re-run
check 739, 2026-08-02, drc_update, gf180mcu-precheck 1.7.3
PDK open_pdks 1.0.604, LibreLane 5fe3db1
KLayout.ReadLayoutpassedpassed
KLayout.CheckTopLevelpassedpassed
KLayout.CheckSizepassedpassed
KLayout.GenerateIDpassedpassed
KLayout.Renderpassedpassed
KLayout.Densitypassedpassed
Checker.KLayoutDensitypassedpassed
KLayout.ZeroAreaPolygonspassedpassed
Checker.KLayoutZeroAreaPolygonspassedpassed
KLayout.Antennapassedpassed
Checker.KLayoutAntennapassedpassed
Magic.DRCpassedpassed
Checker.MagicDRCadvisory warningadvisory warning
KLayout.DRCpassedpassed
Checker.KLayoutDRCpassedpassed
KLayout.WriteLayoutpassedpassed
KLayout DRC errors00
Magic DRC errors (advisory)4,3164,316
Filessteps · log (gzip)steps · log (gzip)

The steps of the gf180mcu-precheck LibreLane flow, as run by platform.wafer.space. The design was accepted on the newest finished check before it was submitted; later re-runs check the same file with updated rules. KLayout DRC is the sign-off check. Magic DRC is advisory: its count does not stop a design. In the logs, Magic's "Error while reading cell" lines about fill cells are messages from its reader, not check failures.

Data and method

Everything on this page is measured from the public layout; the dates come from the published schedules.

  • Logic cells are standard cell instances, excluding fillers, taps, antenna diodes and tie cells.
  • Transistors are places where gate polysilicon crosses diffusion, not counting dummy fill.
  • Core area is the whole project.
  • Bond pads are the pad openings in the pad ring, or in a second ring of pads inside it for chip-on-board bonding; probe pads are the others, next to the blocks they test. Letters and logos on the pad layer are not pads.
  • Theoretical maximum tiles one cell at its placement boundary with no routing.
  • Densest 0.1 mm square is the best 0.1 mm square anywhere in each die, sliding in 20 µm steps and avoiding SRAM, given per mm².

What is Tiny Tapeout?

Tiny Tapeout is the quickest and cheapest way to get your own design made on a real chip.

Many designs share one Tiny Tapeout chip. Each project gets one or more small tiles, and a multiplexer on the chip connects the one you choose to the pins. Draw your first design in the browser with no experience by following the digital design guide, or write it in Verilog or another HDL; Tiny Tapeout's templates build and check it on GitHub. The chip comes on a demo board that selects your design and drives it.

Tiny Tapeout also runs workshops and supports teaching in universities and schools. Browse every Tiny Tapeout chip and the projects proven in silicon, or read the Tiny Tapeout FAQ.

The Tiny Tapeout demo board, with the socket in the middle where the chip's breakout card plugs in
Tiny Tapeout chips come on a breakout card that plugs into the middle of the demo board. Its RP2350 selects a project and drives its clock; the DIP switches, the seven-segment display and the Pmod headers connect to the project's pins. Render: Tiny Tapeout, tt-demo-pcb, Apache 2.0.

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.