Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

7-Segment Neural Predictor

129 · Accelerators · 1 × 2 tiles

by Abdul Hannan A.

Layout render of 7-Segment Neural Predictor

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		29k (39% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		34k (45% of buffer maximum)
Core covered by logic69%
Transistor density
transistors per mm²		289k average, 320k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A small neural network that predicts digits 0-9 from 7-segment display patterns.

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_machinelearning
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 3, row 6 of the tile grid
Mux address129
LanguageVerilog
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors33,388
Logic cells3,389 + 4,050 filler and tap cells
Libraries 7t-5V (3k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

69%
24%
  • Logic cells 0.08 mm² (69%)
  • Filler and tap cells 0.03 mm² (24%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 4992-input NAND gate
xor2_17t-5V 4082-input XOR gate
nor2_17t-5V 3522-input NOR gate
aoi21_17t-5V 213AND-OR-Invert compound gate
oai21_17t-5V 207OR-AND-Invert compound gate
xnor2_17t-5V 1542-input XNOR gate
clkinv_17t-5V 136Clock inverter
xor2_27t-5V 1272-input XOR gate (2x drive)
and2_17t-5V 1052-input AND gate
buf_27t-5V 101Buffer (2x drive)

Logic density map

262 logic cells, 2,701 transistors 299 logic cells, 2,853 transistors 297 logic cells, 2,959 transistors 131 logic cells, 1,272 transistors 319 logic cells, 2,978 transistors 318 logic cells, 3,275 transistors 337 logic cells, 3,172 transistors 147 logic cells, 1,454 transistors 303 logic cells, 3,017 transistors 300 logic cells, 3,137 transistors 306 logic cells, 3,131 transistors 128 logic cells, 1,332 transistors 70 logic cells, 578 transistors 61 logic cells, 610 transistors 69 logic cells, 637 transistors 42 logic cells, 282 transistors Densest SRAM-free 0.1 mm square: 343 logic cells 26k 30k 30k 32k 32k 34k 30k 30k 31k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (34k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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