Tiny Tapeout GF 26a · Die T26A on wafer.space Run 2

Pong in Verilog

386 · Games · 1 × 2 tiles

by Jorobraun, TnTim1, ColdC5

Layout render of Pong in Verilog

Rendered from the layout at 0.33 µm per pixel. Layers: NwellDiffusionPolysiliconMetal 1Metal 2Metal 3Metal 4Metal 5Top metalPad openings

Logic density

Core average
logic cells per mm²		10k (13% of buffer maximum)
Densest 0.1 mm square
logic cells per mm²		28k (37% of buffer maximum)
Core covered by logic26%
Transistor density
transistors per mm²		238k average, 310k in the 0.1 mm square with the most logic cells

Every figure here is measured from the public layout, the same way for every design on the chip: see data and method, and how its designs used the process.

A simple Pong game with VGA-style output

Source repository Its page on Tiny TapeoutBuy a chip and board

Size347 × 325 µm (0.113 mm²)
Macrott_um_main
Filesdocumentation · licence · layout and netlist in Tiny Tapeout GF 26a
Tiles1 × 2 at column 2, row 3 of the tile grid
Mux address386
LanguageVerilog
Clock25.175 MHz
Built withLibreLane 3.0.0, open_pdks 54435919abff
Transistors27,532
Logic cells1,136 + 3,307 filler and tap cells
Libraries 7t-5V (1k)
SRAMNo SRAM

Process features

Which parts of the GF180MCU process this design uses: its transistor voltages and where they come from, its gate oxides, and any devices drawn by hand outside the standard cells, SRAM and pads.

5 V7t-5V standard cells
Gate oxidesThick only (5 V/6 V) in the design itself

Where the area went

How this project's area splits between logic cells, filler and tap cells and other.

26%
67%
  • Logic cells 0.03 mm² (26%)
  • Filler and tap cells 0.08 mm² (67%)
  • Other 0.01 mm² (7%)

Most used cells

The ten standard cells this design uses most.

CellLibraryInstancesWhat it does
nand2_17t-5V 1482-input NAND gate
nor2_17t-5V 892-input NOR gate
dffq_17t-5V 86D flip-flop (1 bit storage)
aoi21_17t-5V 85AND-OR-Invert compound gate
oai21_17t-5V 70OR-AND-Invert compound gate
clkinv_17t-5V 63Clock inverter
xor2_17t-5V 432-input XOR gate
nand3_17t-5V 343-input NAND gate
aoi22_17t-5V 29AND-OR-Invert (2x2 inputs)
or2_17t-5V 222-input OR gate

Logic density map

0 logic cells, 2,031 transistors 0 logic cells, 2,128 transistors 0 logic cells, 2,105 transistors 0 logic cells, 882 transistors 2 logic cells, 2,119 transistors 67 logic cells, 2,384 transistors 166 logic cells, 2,752 transistors 55 logic cells, 1,190 transistors 111 logic cells, 2,485 transistors 221 logic cells, 3,054 transistors 250 logic cells, 3,085 transistors 115 logic cells, 1,268 transistors 26 logic cells, 500 transistors 48 logic cells, 640 transistors 47 logic cells, 621 transistors 28 logic cells, 288 transistors Densest SRAM-free 0.1 mm square: 278 logic cells 0 0 0 <1k 7k 17k 11k 22k 25k

Logic cells per mm² in each 0.1 mm square of the project (counted in the square, scaled up to a mm²). Hatched outlines are SRAM macros; the red outline is the densest 0.1 mm square that avoids them (28k logic cells per mm²), found by sliding a 0.1 mm square over the project in 20 µm steps, so it can straddle the fixed squares and find more than any one of them. Squares at the edges are partial, so they read low.

Want your own design on a chip like this one?

Start with a tile: the next Tiny Tapeout GF180MCU chips take projects until 7 December 2026, for wafer.space Run 3. For a die of your own, wafer.space Run 3 takes orders until 9 December 2026.

Submit a project

Tiny Tapeout and wafer.space are independent companies that work together (announcement). Tiny Tapeout runs its own shuttles: it takes the projects, builds the die, and sells and supports the chips and boards. wafer.space has the dies manufactured on its GF180MCU runs, and these pages are wafer.space's measurements of them. For anything about a Tiny Tapeout project, chip or order, contact Tiny Tapeout.

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